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From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Mingchuang Qiao <mingchuang.qiao@mediatek.com>
Cc: kerun.zhu@mediatek.com, linux-pci@vger.kernel.org,
	lambert.wang@mediatek.com, rjw@rjwysocki.net,
	linux-kernel@vger.kernel.org, matthias.bgg@gmail.com,
	alex.williamson@redhat.com, linux-mediatek@lists.infradead.org,
	utkarsh.h.patel@intel.com, haijun.liu@mediatek.com,
	bhelgaas@google.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [v3] PCI: Avoid unsync of LTR mechanism configuration
Date: Wed, 3 Feb 2021 10:05:18 +0200	[thread overview]
Message-ID: <20210203080518.GP2542@lahna.fi.intel.com> (raw)
In-Reply-To: <1612318441.5980.142.camel@mcddlt001>

On Wed, Feb 03, 2021 at 10:14:01AM +0800, Mingchuang Qiao wrote:
> Hi,
> 
> On Mon, 2021-02-01 at 13:32 +0200, Mika Westerberg wrote:
> > Hi,
> > 
> > On Fri, Jan 29, 2021 at 03:11:37PM +0800, mingchuang.qiao@mediatek.com wrote:
> > > From: Mingchuang Qiao <mingchuang.qiao@mediatek.com>
> > > 
> > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is
> > > configured in pci_configure_ltr(). If device and bridge both support LTR
> > > mechanism, the "LTR Mechanism Enable" bit of device and bridge will be
> > > enabled in DEVCTL2 register. And pci_dev->ltr_path will be set as 1.
> > > 
> > > If PCIe link goes down when device resets, the "LTR Mechanism Enable" bit
> > > of bridge will change to 0 according to PCIe r5.0, sec 7.5.3.16. However,
> > > the pci_dev->ltr_path value of bridge is still 1.
> > > 
> > > For following conditions, check and re-configure "LTR Mechanism Enable" bit
> > > of bridge to make "LTR Mechanism Enable" bit mtach ltr_path value.
> > 
> > Typo mtach -> match.
> > 
> > >    -before configuring device's LTR for hot-remove/hot-add
> > >    -before restoring device's DEVCTL2 register when restore device state
> > > 
> > > Signed-off-by: Mingchuang Qiao <mingchuang.qiao@mediatek.com>
> > > ---
> > > changes of v2
> > >  -modify patch description
> > >  -reconfigure bridge's LTR before restoring device DEVCTL2 register
> > > changes of v3
> > >  -call pci_reconfigure_bridge_ltr() in probe.c
> > 
> > Hmm, which part of this patch takes care of the reset path? It is not
> > entirely clear to me at least.
> > 
> 
> When device resets and link goes down, there seems to have two methods
> to recover for software. 
>    -One is that trigger device removal and rescan.
>    -The other is that restore device with pci_restore_state() after link
> comes back up.
> For above both scenarios, we need check and reconfigure "LTR Mechanism
> Enable" bit of bridge. It's also this patch intends to do.
>    -For the rescan scenario, it's done in pci_configure_ltr().
>    -For the restore scenario, it's done in pci_restore_pcie_state().

Okay, thanks for the clarification!

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      reply	other threads:[~2021-02-03  8:06 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-29  7:11 [v3] PCI: Avoid unsync of LTR mechanism configuration mingchuang.qiao
2021-02-01 11:32 ` Mika Westerberg
2021-02-03  2:14   ` Mingchuang Qiao
2021-02-03  8:05     ` Mika Westerberg [this message]

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