From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5F01C433E0 for ; Wed, 3 Feb 2021 13:44:42 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 846FB64F4E for ; Wed, 3 Feb 2021 13:44:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 846FB64F4E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vyalcI2VAbsJAJ92/1lF6nv5ZjuBx6Xe9s/zz2nNwY0=; b=po8ssS/XIL8XHj8lyjpgGfl8G gWdBPSQJ9PjjqwQuFNG8btwBQVYqlCP640LwGqTP7QkmLh+QD6WWkOSHaQ6iMFtS/tBXGULSg8fdo SfQ6lb6cmfW1MrHv63qJRnTl9QMGIvgSkAvKEgLfabyUSpdLitLLjGKhile4Q7mOAa4PRCfP7izf9 SzdKZYb85zRVwfMkWvfX2nP6l07n9021t+St3cHHo8yWJT4gzWTmPx/3Uznzr4GP0MIkuQt2Xp2c/ SoU29EavRC38cZ/szNkyOBOgVk/gshOUzj2QB9+fCR7RZH41GMLw7XZO/BR8tAnLsHB2gB1wKnmOx 7YOHrV/bQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7IRO-0006Ya-Pw; Wed, 03 Feb 2021 13:43:30 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7IRM-0006Xr-6n for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2021 13:43:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BBA9DD6E; Wed, 3 Feb 2021 05:43:23 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.11.206]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 426483F73B; Wed, 3 Feb 2021 05:43:22 -0800 (PST) Date: Wed, 3 Feb 2021 13:43:19 +0000 From: Mark Rutland To: Shaokun Zhang Subject: Re: [PATCH v2 7/8] drivers/perf: hisi: Add support for HiSilicon PA PMU driver Message-ID: <20210203134319.GM55896@C02TD0UTHF1T.local> References: <1612338668-40493-1-git-send-email-zhangshaokun@hisilicon.com> <1612338668-40493-8-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1612338668-40493-8-git-send-email-zhangshaokun@hisilicon.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210203_084328_322883_E0FB9F02 X-CRM114-Status: GOOD ( 19.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Qi Liu , John Garry , Will Deacon , linux-arm-kernel@lists.infradead.org, Jonathan Cameron Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Feb 03, 2021 at 03:51:07PM +0800, Shaokun Zhang wrote: > On HiSilicon Hip09 platform, there is a PA (Protocol Adapter) module on > each chip SICL (Super I/O Cluster) which incorporates three Hydra interface > and facilitates the cache coherency between the dies on the chip. While PA > uncore PMU model is the same as other Hip09 PMU modules and many PMU events > are supported. Let's support the PMU driver using the HiSilicon uncore PMU > framework. > +HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_cmd, config1, 10, 0); > +HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_msk, config1, 21, 11); > +HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 32, 22); > +HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 43, 33); > +HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 44, 44); As with the other patches, a brief introduction for these in the commit message would be helpful. > +static void hisi_pa_pmu_enable_filter(struct perf_event *event) > +{ > + if (event->attr.config1 != 0x0) { > + hisi_pa_pmu_enable_tracetag(event); > + hisi_pa_pmu_config_srcid(event); > + hisi_pa_pmu_config_tgtid(event); > + } > +} > + > +static void hisi_pa_pmu_disable_filter(struct perf_event *event) > +{ > + if (event->attr.config1 != 0x0) { > + hisi_pa_pmu_clear_tgtid(event); > + hisi_pa_pmu_clear_srcid(event); > + hisi_pa_pmu_clear_tracetag(event); > + } > +} Does this get reset when the driver probes? I couldn't spot where we ensured this was in a sane initial state. > +static void hisi_pa_pmu_write_evtype(struct hisi_pmu *pa_pmu, int idx, > + u32 type) > +{ > + u32 reg, reg_idx, shift, val; > + > + /* > + * Select the appropriate event select register(PA_EVENT_TYPE0/1). > + * There are 2 event select registers for the 8 hardware counters. > + * Event code is 8-bits and for the former 4 hardware counters, > + * PA_EVENT_TYPE0 is chosen. For the latter 4 hardware counters, > + * PA_EVENT_TYPE1 is chosen. > + */ > + reg = PA_EVENT_TYPE0 + rounddown(idx, 4); The use of rounddown() here is confusing, as it relies on the number of elements per register happening to be equal to the size of the register in bytes. That works here since each element is a byte, but as it's not the common case it sticks out. Please divide the index by the number of elements per register, then multiply that by the size of the register. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel