* [PATCH 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654
@ 2021-03-01 19:58 Pratyush Yadav
2021-03-01 19:58 ` [PATCH 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI Pratyush Yadav
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Pratyush Yadav @ 2021-03-01 19:58 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel,
devicetree, linux-kernel
Cc: Pratyush Yadav, Vignesh Raghavendra
Hi,
Now that the OSPI controller driver and the SPI NOR core have support
for 8D-8D-8D mode, the device tree can be updated to allow Octal DTR
transactions.
Pratyush Yadav (3):
arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI
arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI
arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 4 +--
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 +--
4 files changed, 57 insertions(+), 4 deletions(-)
--
2.30.0
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI
2021-03-01 19:58 [PATCH 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Pratyush Yadav
@ 2021-03-01 19:58 ` Pratyush Yadav
2021-03-01 19:58 ` [PATCH 2/3] arm64: dts: ti: am654-base-board: " Pratyush Yadav
2021-03-01 19:58 ` [PATCH 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 Pratyush Yadav
2 siblings, 0 replies; 6+ messages in thread
From: Pratyush Yadav @ 2021-03-01 19:58 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel,
devicetree, linux-kernel
Cc: Pratyush Yadav, Vignesh Raghavendra
Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the
frequency to 25 MHz. This is the frequency that the flash has been
successfully tested with in Octal DTR mode. The total performance should
still increase since 8D-8D-8D mode should be at least twice as fast as
1S-1S-8S mode.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 57720e6a04c5..2fee2906183d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -174,9 +174,9 @@ &ospi0 {
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
- spi-max-frequency = <40000000>;
+ spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
--
2.30.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI
2021-03-01 19:58 [PATCH 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Pratyush Yadav
2021-03-01 19:58 ` [PATCH 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI Pratyush Yadav
@ 2021-03-01 19:58 ` Pratyush Yadav
2021-03-01 19:58 ` [PATCH 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 Pratyush Yadav
2 siblings, 0 replies; 6+ messages in thread
From: Pratyush Yadav @ 2021-03-01 19:58 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel,
devicetree, linux-kernel
Cc: Pratyush Yadav, Vignesh Raghavendra
Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the
frequency to 25 MHz. This is the frequency that the flash has been
successfully tested with in Octal DTR mode. The total performance should
still increase since 8D-8D-8D mode should be at least twice as fast as
1S-1S-8S mode.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index fe3043943906..9e87fb313a54 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -483,9 +483,9 @@ &ospi0 {
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
- spi-tx-bus-width = <1>;
+ spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
- spi-max-frequency = <40000000>;
+ spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
--
2.30.0
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0
2021-03-01 19:58 [PATCH 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Pratyush Yadav
2021-03-01 19:58 ` [PATCH 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI Pratyush Yadav
2021-03-01 19:58 ` [PATCH 2/3] arm64: dts: ti: am654-base-board: " Pratyush Yadav
@ 2021-03-01 19:58 ` Pratyush Yadav
2021-03-02 7:40 ` Vignesh Raghavendra
2 siblings, 1 reply; 6+ messages in thread
From: Pratyush Yadav @ 2021-03-01 19:58 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel,
devicetree, linux-kernel
Cc: Pratyush Yadav, Vignesh Raghavendra
TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++
2 files changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 359e3e8a8cd0..5408ec815d58 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -269,6 +269,23 @@ hbmc: hyperbus@47034000 {
#size-cells = <1>;
mux-controls = <&hbmc_mux 0>;
};
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi";
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x5 0x00000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 103 0>;
+ assigned-clocks = <&k3_clks 103 0>;
+ assigned-clock-parents = <&k3_clks 103 2>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
tscadc0: tscadc@40200000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index a988e2ab2ba1..effecf852139 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -100,6 +100,22 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
};
+
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
+ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
+ J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
+ J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
+ J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
+ J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
+ J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
+ J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
+ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
+ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
+ J721E_WKUP_IOPAD(0x0008, PIN_INPUT_PULLDOWN, 0) /* MCU_OSPI0_DQS */
+ >;
+ };
};
&main_pmx0 {
@@ -235,3 +251,23 @@ exp_som: gpio@21 {
"GPIO_LIN_EN", "CAN_STB";
};
};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
--
2.30.0
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0
2021-03-01 19:58 ` [PATCH 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 Pratyush Yadav
@ 2021-03-02 7:40 ` Vignesh Raghavendra
2021-03-02 12:05 ` Pratyush Yadav
0 siblings, 1 reply; 6+ messages in thread
From: Vignesh Raghavendra @ 2021-03-02 7:40 UTC (permalink / raw)
To: Pratyush Yadav, Nishanth Menon, Tero Kristo, Rob Herring,
linux-arm-kernel, devicetree, linux-kernel
On 3/2/21 1:28 AM, Pratyush Yadav wrote:
> +
> + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
> + pinctrl-single,pins = <
> + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
> + J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
> + J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
> + J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
> + J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
> + J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
> + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
> + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
> + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
> + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
> + J721E_WKUP_IOPAD(0x0008, PIN_INPUT_PULLDOWN, 0) /* MCU_OSPI0_DQS */
> + >;
> + };
There is a pulldown resistor on the board right? So, internal pulldown
is unnecessary and may even cause conflicts.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0
2021-03-02 7:40 ` Vignesh Raghavendra
@ 2021-03-02 12:05 ` Pratyush Yadav
0 siblings, 0 replies; 6+ messages in thread
From: Pratyush Yadav @ 2021-03-02 12:05 UTC (permalink / raw)
To: Vignesh Raghavendra
Cc: Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel,
devicetree, linux-kernel
On 02/03/21 01:10PM, Vignesh Raghavendra wrote:
>
>
> On 3/2/21 1:28 AM, Pratyush Yadav wrote:
> > +
> > + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
> > + pinctrl-single,pins = <
> > + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
> > + J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
> > + J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
> > + J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
> > + J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
> > + J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
> > + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
> > + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
> > + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
> > + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
> > + J721E_WKUP_IOPAD(0x0008, PIN_INPUT_PULLDOWN, 0) /* MCU_OSPI0_DQS */
> > + >;
> > + };
>
> There is a pulldown resistor on the board right? So, internal pulldown
> is unnecessary and may even cause conflicts.
Right. Will fix.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-03-03 21:54 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-01 19:58 [PATCH 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Pratyush Yadav
2021-03-01 19:58 ` [PATCH 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI Pratyush Yadav
2021-03-01 19:58 ` [PATCH 2/3] arm64: dts: ti: am654-base-board: " Pratyush Yadav
2021-03-01 19:58 ` [PATCH 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 Pratyush Yadav
2021-03-02 7:40 ` Vignesh Raghavendra
2021-03-02 12:05 ` Pratyush Yadav
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