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Sun, 07 Mar 2021 19:02:24 -0800 Received: from mtkmbs05n1.mediatek.inc (172.21.101.15) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 7 Mar 2021 19:01:34 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 8 Mar 2021 11:01:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 8 Mar 2021 11:01:33 +0800 From: Mark-PK Tsai To: , Mark-PK Tsai CC: , , , , , , , Subject: Re: [PATCH] irqchip/irq-mst: Support polarity configuration Date: Mon, 8 Mar 2021 11:01:01 +0800 Message-ID: <20210308030102.5161-1-mark-pk.tsai@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <874khorux9.wl-maz@kernel.org> References: <874khorux9.wl-maz@kernel.org> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_030256_266319_E458E63C X-CRM114-Status: GOOD ( 21.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Marc Zyngier > > > > Support irq polarity configuration and save and restore the config > > when system suspend and resume. > > > > Signed-off-by: Mark-PK Tsai > > --- > > drivers/irqchip/irq-mst-intc.c | 87 ++++++++++++++++++++++++++++++++-- > > 1 file changed, 84 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/irqchip/irq-mst-intc.c b/drivers/irqchip/irq-mst-intc.c > > index 143657b0cf28..979a4d55bcb1 100644 > > --- a/drivers/irqchip/irq-mst-intc.c > > +++ b/drivers/irqchip/irq-mst-intc.c > > @@ -13,15 +13,25 @@ > > #include > > #include > > #include > > +#include > > > > -#define INTC_MASK 0x0 > > -#define INTC_EOI 0x20 > > +#define INTC_MASK 0x0 > > +#define INTC_REV_POLARITY 0x10 > > +#define INTC_EOI 0x20 > > + > > +#ifdef CONFIG_PM_SLEEP > > +static LIST_HEAD(mst_intc_list); > > +#endif > > > > struct mst_intc_chip_data { > > raw_spinlock_t lock; > > unsigned int irq_start, nr_irqs; > > void __iomem *base; > > bool no_eoi; > > +#ifdef CONFIG_PM_SLEEP > > + struct list_head entry; > > + u16 saved_polarity_conf[DIV_ROUND_UP(64, 16)]; > > Where is this 64 coming from? The maximum number of interrupts a mst-intc supports is 64 in Mstar and Mediatek SoCs now. So I just use the maximum number of interrupts here. > > > +#endif > > }; > > > > static void mst_set_irq(struct irq_data *d, u32 offset) > > @@ -78,6 +88,16 @@ static void mst_intc_eoi_irq(struct irq_data *d) > > irq_chip_eoi_parent(d); > > } > > > > +static int mst_irq_chip_set_type(struct irq_data *data, unsigned int type) > > +{ > > + if (type == IRQ_TYPE_LEVEL_LOW) { > > + mst_set_irq(data, INTC_REV_POLARITY); > > + type = IRQ_TYPE_LEVEL_HIGH; > > + } > > If you are introducing a irq_set_type callback, you need to return an > error for the settings you don't handle. Got it, thanks for the comment. I will add it in the next patch. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel