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Mon, 08 Mar 2021 10:45:59 -0800 (PST) Received: from robh.at.kernel.org ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id y11sm6330111ilv.64.2021.03.08.10.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 10:45:59 -0800 (PST) Received: (nullmailer pid 2770740 invoked by uid 1000); Mon, 08 Mar 2021 18:45:57 -0000 Date: Mon, 8 Mar 2021 11:45:57 -0700 From: Rob Herring To: Claudiu Beznea Subject: Re: [PATCH 1/2] dt-bindings: mchp-eic: add bindings Message-ID: <20210308184557.GA2768020@robh.at.kernel.org> References: <20210302102846.619980-1-claudiu.beznea@microchip.com> <20210302102846.619980-2-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210302102846.619980-2-claudiu.beznea@microchip.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_184604_002231_CC1D4A5B X-CRM114-Status: GOOD ( 21.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, maz@kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 02, 2021 at 12:28:45PM +0200, Claudiu Beznea wrote: > Add DT bindings for Microchip External Interrupt Controller. > > Signed-off-by: Claudiu Beznea > --- > .../interrupt-controller/mchp,eic.yaml | 74 +++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml > new file mode 100644 > index 000000000000..5a927817aa7d > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/mchp,eic.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip External Interrupt Controller > + > +maintainers: > + - Claudiu Beznea > + > +description: > + This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides > + support for handling up to 2 external interrupt lines. > + > +properties: > + compatible: > + enum: > + - microchip,sama7g5-eic > + > + reg: > + maxItems: 1 > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 3 > + description: > + The first cell is the input IRQ number (between 0 and 1), the second cell > + is the trigger type as defined in interrupt.txt present in this directory > + and the third cell is the glitch filter (1, 2, 4, 8) in clock cycles > + > + 'interrupts': Don't need quotes here. > + description: | > + Contains the GIC SPI IRQs mapped to the external interrupt lines. They > + should be specified sequentially from output 0 to output 1. > + minItems: 2 > + maxItems: 2 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: pclk > + > +required: > + - compatible > + - reg > + - interrupt-controller > + - '#interrupt-cells' > + - 'interrupts' Or here. > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + eic: eic@e1628000 { interrupt-controller@... > + compatible = "microchip,sama7g5-eic"; > + reg = <0xe1628000 0x100>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = , > + ; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; > + clock-names = "pclk"; > + }; > + > +... > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel