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Tue, 09 Mar 2021 14:38:58 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lJdVa-004rJ8-17 for linux-arm-kernel@lists.infradead.org; Tue, 09 Mar 2021 14:38:54 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 90F0464EEE; Tue, 9 Mar 2021 14:38:45 +0000 (UTC) Date: Tue, 9 Mar 2021 14:38:42 +0000 From: Catalin Marinas To: Will Deacon Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, kernel-team@android.com, James Morse , Julien Thierry , Suzuki K Poulose , Mark Rutland , Alexandru Elisei Subject: Re: [PATCH] KVM: arm64: Ensure I-cache isolation between vcpus of a same VM Message-ID: <20210309143841.GA32754@arm.com> References: <20210303164505.68492-1-maz@kernel.org> <20210309132645.GA28297@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210309132645.GA28297@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210309_143850_396574_FC032C9F X-CRM114-Status: GOOD ( 22.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 09, 2021 at 01:26:46PM +0000, Will Deacon wrote: > On Wed, Mar 03, 2021 at 04:45:05PM +0000, Marc Zyngier wrote: > > It recently became apparent that the ARMv8 architecture has interesting > > rules regarding attributes being used when fetching instructions > > if the MMU is off at Stage-1. > > > > In this situation, the CPU is allowed to fetch from the PoC and > > allocate into the I-cache (unless the memory is mapped with > > the XN attribute at Stage-2). > > > > If we transpose this to vcpus sharing a single physical CPU, > > it is possible for a vcpu running with its MMU off to influence > > another vcpu running with its MMU on, as the latter is expected to > > fetch from the PoU (and self-patching code doesn't flush below that > > level). > > > > In order to solve this, reuse the vcpu-private TLB invalidation > > code to apply the same policy to the I-cache, nuking it every time > > the vcpu runs on a physical CPU that ran another vcpu of the same > > VM in the past. > > > > This involve renaming __kvm_tlb_flush_local_vmid() to > > __kvm_flush_cpu_context(), and inserting a local i-cache invalidation > > there. > > > > Cc: stable@vger.kernel.org > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/kvm_asm.h | 4 ++-- > > arch/arm64/kvm/arm.c | 7 ++++++- > > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 6 +++--- > > arch/arm64/kvm/hyp/nvhe/tlb.c | 3 ++- > > arch/arm64/kvm/hyp/vhe/tlb.c | 3 ++- > > 5 files changed, 15 insertions(+), 8 deletions(-) > > Since the FWB discussion doesn't affect the correctness of this patch: > > Acked-by: Will Deacon I agree. We can optimise it later for FWB. Acked-by: Catalin Marinas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel