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Mon, 15 Mar 2021 21:17:46 -0700 (PDT) Date: Tue, 16 Mar 2021 09:47:39 +0530 From: Manivannan Sadhasivam To: Cristian Ciocaltea Cc: Stephen Boyd , Rob Herring , Andreas =?iso-8859-1?Q?F=E4rber?= , Michael Turquette , Edgar Bernardi Righi , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 3/6] clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC Message-ID: <20210316041739.GC1798@thinkpad> References: <13576ddb604a9097603d95cd2605275c20fb2f56.1615221459.git.cristian.ciocaltea@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <13576ddb604a9097603d95cd2605275c20fb2f56.1615221459.git.cristian.ciocaltea@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210316_041749_809537_157632E5 X-CRM114-Status: GOOD ( 28.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 08, 2021 at 07:18:28PM +0200, Cristian Ciocaltea wrote: > The following clocks of the Actions Semi Owl S500 SoC have been defined > to use a shared clock factor table 'bisp_factor_table[]': DE[1-2], VCE, > VDE, BISP, SENSOR[0-1] > > There are several issues involved in this approach: > > * 'bisp_factor_table[]' describes the configuration of a regular 8-rates > divider, so its usage is redundant. Additionally, judging by the BISP > clock context, it is incomplete since it maps only 8 out of 12 > possible entries. > > * The clocks mentioned above are not identical in terms of the available > rates, therefore cannot rely on the same factor table. Specifically, > BISP and SENSOR* are standard 12-rate dividers so their configuration > should rely on a proper clock div table, while VCE and VDE require a > factor table that is a actually a subset of the one needed for DE[1-2] > clocks. > > Let's fix this by implementing the following: > > * Add new factor tables 'de_factor_table' and 'hde_factor_table' to > properly handle DE[1-2], VCE and VDE clocks. > > * Add a common div table 'std12rate_div_table' for BISP and SENSOR[0-1] > clocks converted to OWL_COMP_DIV. > > * Drop the now unused 'bisp_factor_table[]'. > Nice! > Additionally, since SENSOR[0-1] are not gated, unset the OWL_GATE_HW > configuration and drop the CLK_IGNORE_UNUSED flag in their definitions. > No. You should not screen the functionality exposed by the hw, that's what the purpose of these CLK_ flags. Other than that, this patch looks good to me. > Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") > Signed-off-by: Cristian Ciocaltea > --- > drivers/clk/actions/owl-s500.c | 48 ++++++++++++++++++++++------------ > 1 file changed, 31 insertions(+), 17 deletions(-) > > diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c > index 69cd959205f5..abe8874353de 100644 > --- a/drivers/clk/actions/owl-s500.c > +++ b/drivers/clk/actions/owl-s500.c > @@ -138,9 +138,16 @@ static struct clk_factor_table sd_factor_table[] = { > { 0, 0, 0 }, > }; > > -static struct clk_factor_table bisp_factor_table[] = { > - { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 }, > - { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 }, > +static struct clk_factor_table de_factor_table[] = { > + { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, > + { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, > + { 8, 1, 12 }, > + { 0, 0, 0 }, > +}; > + > +static struct clk_factor_table hde_factor_table[] = { > + { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, > + { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, > { 0, 0, 0 }, > }; > > @@ -154,6 +161,13 @@ static struct clk_div_table rmii_ref_div_table[] = { > { 0, 0 }, > }; > > +static struct clk_div_table std12rate_div_table[] = { > + { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, > + { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, > + { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, > + { 0, 0 }, > +}; > + > static struct clk_div_table i2s_div_table[] = { > { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, > { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 }, > @@ -189,39 +203,39 @@ static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNE > > /* factor clocks */ > static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0); > -static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0); > -static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0); > +static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0); > +static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); > > /* composite clocks */ > static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p, > OWL_MUX_HW(CMU_VCECLK, 4, 2), > OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0), > - OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table), > + OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table), > 0); > > static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p, > OWL_MUX_HW(CMU_VDECLK, 4, 2), > OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0), > - OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table), > + OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table), > 0); > > -static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p, > +static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p, > OWL_MUX_HW(CMU_BISPCLK, 4, 1), > OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), > - OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table), > + OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table), > 0); > > -static OWL_COMP_FACTOR(sensor0_clk, "sensor0_clk", sensor_clk_mux_p, > +static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p, > OWL_MUX_HW(CMU_SENSORCLK, 4, 1), > - OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), > - OWL_FACTOR_HW(CMU_SENSORCLK, 0, 3, 0, bisp_factor_table), > - CLK_IGNORE_UNUSED); > + { 0 }, > + OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table), > + 0); > > -static OWL_COMP_FACTOR(sensor1_clk, "sensor1_clk", sensor_clk_mux_p, > +static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p, > OWL_MUX_HW(CMU_SENSORCLK, 4, 1), > - OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), > - OWL_FACTOR_HW(CMU_SENSORCLK, 8, 3, 0, bisp_factor_table), > - CLK_IGNORE_UNUSED); > + { 0 }, > + OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table), > + 0); > > static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p, > OWL_MUX_HW(CMU_SD0CLK, 9, 1), > -- > 2.30.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel