From: quanyang.wang@windriver.com
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Michal Simek <michal.simek@xilinx.com>
Cc: Rajan Vaja <rajan.vaja@xilinx.com>,
Jolly Shah <jolly.shah@xilinx.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Quanyang Wang <quanyang.wang@windriver.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 1/2] clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
Date: Fri, 19 Mar 2021 18:07:17 +0800 [thread overview]
Message-ID: <20210319100717.507500-1-quanyang.wang@windriver.com> (raw)
From: Quanyang Wang <quanyang.wang@windriver.com>
If there is a IOCTL_SET_PLL_FRAC_MODE request sent to ATF ever,
we shouldn't skip invoking PM_CLOCK_ENABLE fn even though this
pll has been enabled. In ATF implementation, it will only assign
the mode to the variable (struct pm_pll *)pll->mode when handling
IOCTL_SET_PLL_FRAC_MODE call. Invoking PM_CLOCK_ENABLE can force
ATF send request to PWU to set the pll mode to PLL's register.
There is a scenario that happens in enabling VPLL_INT(clk_id:96):
1) VPLL_INT has been enabled during booting.
2) A driver calls clk_set_rate and according to the rate, the VPLL_INT
should be set to FRAC mode. Then zynqmp_pll_set_mode is called
to pass IOCTL_SET_PLL_FRAC_MODE to ATF. Note that at this point
ATF just stores the mode to a variable.
3) This driver calls clk_prepare_enable and zynqmp_pll_enable is
called to try to enable VPLL_INT pll. Because of 1), the function
zynqmp_pll_enable just returns without doing anything after checking
that this pll has been enabled.
In the scenario above, the pll mode of VPLL_INT will never be set
successfully. So adding set_pll_mode to chec condition to fix it.
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
---
drivers/clk/zynqmp/pll.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index 92f449ed38e5..f1e8f37d7f52 100644
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -14,10 +14,12 @@
* struct zynqmp_pll - PLL clock
* @hw: Handle between common and hardware-specific interfaces
* @clk_id: PLL clock ID
+ * @set_pll_mode: Whether an IOCTL_SET_PLL_FRAC_MODE request be sent to ATF
*/
struct zynqmp_pll {
struct clk_hw hw;
u32 clk_id;
+ bool set_pll_mode;
};
#define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
@@ -81,6 +83,8 @@ static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
if (ret)
pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
__func__, clk_name, ret);
+ else
+ clk->set_pll_mode = true;
}
/**
@@ -240,9 +244,14 @@ static int zynqmp_pll_enable(struct clk_hw *hw)
u32 clk_id = clk->clk_id;
int ret;
- if (zynqmp_pll_is_enabled(hw))
+ /* Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request
+ * that has been sent to ATF.
+ */
+ if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode))
return 0;
+ clk->set_pll_mode = false;
+
ret = zynqmp_pm_clock_enable(clk_id);
if (ret)
pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
--
2.25.1
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next reply other threads:[~2021-03-19 10:25 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-19 10:07 quanyang.wang [this message]
2021-03-21 0:01 ` [PATCH 1/2] clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable Laurent Pinchart
2021-03-22 12:21 ` quanyang.wang
2021-03-30 12:18 ` quanyang.wang
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