From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEFF5C433B4 for ; Mon, 26 Apr 2021 11:50:32 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3CD8F60232 for ; Mon, 26 Apr 2021 11:50:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3CD8F60232 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=HjETrkWerSYIsy1sToxJCHobcHAfxu/5c2LCxwlJ/r4=; b=diwij+shkvk5BJVI1ksp5IJvu 9P6sFW9ksJ2PPNBRuNO3yQAoODvdobZgLeCR3xn8lrEOQndbbWRNq+8Ze/yHxQYQUt6O0JVwW9+oo E1gHbgT1M8IiY9GYH/W1QiS89HobzCiL1SEUhfbRw4vUF9y9Rpj4uvwM62vvRslWK3jZCJwzQmN+G V8lzjjDvxL+lCgIAkPgWeyaXsJwmJsHgr6knsLotcB8xjH8v4vDX2sciXl+/Ere26ng31/zmC2Tre aBZRRfhXbXGa3VbZMt6Do15kJQhd6NrKzS7gC7iUdyqBgWtVQcXYolgqrVYONAmP2vGrKDvQWyE++ MkqdyfbtQ==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lazjc-007Ws3-6O; Mon, 26 Apr 2021 11:49:04 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lazjZ-007WqL-9i for linux-arm-kernel@desiato.infradead.org; Mon, 26 Apr 2021 11:49:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Subject:Cc:To: From:Date:Sender:Reply-To:Content-ID:Content-Description; bh=iYMbLasWpZDnM+fITjFIXrn/LYnrLZTjitG8JKreRPA=; b=3T634me1EgYxjbe9tXkpffUQGT Ozjdcz6NZbeBEVhZJDE4cjvvC/MaHTrnF1uBKFrwNhTOIWNnTOIJSbbQxAsA4u/8T1vPG7JXHjlO+ DdSlAPTlN0lKOZGjMYyYZYCeLyUpu7EOfEHrLdPy0cVzTWHKcZ0OWQ98FYpcHosv9bZGI6cqv/Ywq gNgoPpM4G5BwWOdIc3SzyXmiITMKwIkp6mJ/n5X7XsC462cIwPaEULXSumSyG/rTnUj+QNJA3+Opr RU029Mg+ruzfZF2f/wOXrt5biRlU/V9q9Av7c3+WTeSkO4iZaNc//LbMt8vYfEEWGZmMHol0RjnYy i5iVgERA==; Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lazjV-00Fvya-Lu for linux-arm-kernel@lists.infradead.org; Mon, 26 Apr 2021 11:48:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB4011FB; Mon, 26 Apr 2021 04:48:52 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 273B73F70D; Mon, 26 Apr 2021 04:48:52 -0700 (PDT) Date: Mon, 26 Apr 2021 12:48:18 +0100 From: Andre Przywara To: Jaxson Han Cc: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, wei.chen@arm.com Subject: Re: [boot-wrapper PATCH 3/5] gic-v3: Prepare for gicv3 with EL2 Message-ID: <20210426124818.28a57afa@slackpad.fritz.box> In-Reply-To: <20210420072438.183086-4-jaxson.han@arm.com> References: <20210420072438.183086-1-jaxson.han@arm.com> <20210420072438.183086-4-jaxson.han@arm.com> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210426_044857_847532_0067BC60 X-CRM114-Status: GOOD ( 16.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 20 Apr 2021 15:24:36 +0800 Jaxson Han wrote: > This is a preparation for allowing boot-wrapper configuring the gicv3 > with EL2. The GIC is always confusing, so can you please give some more background here? The introduction of ICC_SRE_EL2 looks straight-forward enough, but the change to the ICC_CTLR_RESET register deserves some comments, I guess. Cheers, Andre > Signed-off-by: Jaxson Han > --- > arch/aarch32/include/asm/gic-v3.h | 7 ++++++ > arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++--- > gic-v3.c | 2 +- > 3 files changed, 43 insertions(+), 4 deletions(-) > > diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h > index ec9a327..86abe09 100644 > --- a/arch/aarch32/include/asm/gic-v3.h > +++ b/arch/aarch32/include/asm/gic-v3.h > @@ -9,6 +9,8 @@ > #ifndef __ASM_AARCH32_GICV3_H > #define __ASM_AARCH32_GICV3_H > > +#define ICC_CTLR_RESET (0UL) > + > static inline uint32_t gic_read_icc_sre(void) > { > uint32_t val; > @@ -26,4 +28,9 @@ static inline void gic_write_icc_ctlr(uint32_t val) > asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val)); > } > > +static inline void gic_init_icc_ctlr() > +{ > + gic_write_icc_ctlr(ICC_CTLR_RESET); > +} > + > #endif > diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h > index e743c02..b3dfbd3 100644 > --- a/arch/aarch64/include/asm/gic-v3.h > +++ b/arch/aarch64/include/asm/gic-v3.h > @@ -15,21 +15,53 @@ > #define ICC_CTLR_EL3 "S3_6_C12_C12_4" > #define ICC_PMR_EL1 "S3_0_C4_C6_0" > > +#define ICC_CTLR_EL3_RESET (0UL) > +#define ICC_CTLR_EL1_RESET (0UL) > + > +static inline uint32_t current_el(void) > +{ > + uint32_t val; > + > + asm volatile ("mrs %0, CurrentEL" : "=r" (val)); > + return val; > +} > + > static inline uint32_t gic_read_icc_sre(void) > { > uint32_t val; > - asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val)); > + > + if(current_el() == CURRENTEL_EL3) > + asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val)); > + else > + asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val)); > + > return val; > } > > static inline void gic_write_icc_sre(uint32_t val) > { > - asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); > + if(current_el() == CURRENTEL_EL3) > + asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); > + else > + asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val)); > } > > -static inline void gic_write_icc_ctlr(uint32_t val) > +static inline void gic_write_icc_ctlr_el3(uint32_t val) > { > asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val)); > } > > +static inline void gic_write_icc_ctlr_el1(uint32_t val) > +{ > + asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val)); > +} > + > +static inline void gic_init_icc_ctlr() > +{ > + if(current_el() == CURRENTEL_EL3) > + gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET); > + else > + gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET); > +} > + > #endif > diff --git a/gic-v3.c b/gic-v3.c > index ae2d2bc..4850572 100644 > --- a/gic-v3.c > +++ b/gic-v3.c > @@ -121,6 +121,6 @@ void gic_secure_init(void) > gic_write_icc_sre(sre); > isb(); > > - gic_write_icc_ctlr(0); > + gic_init_icc_ctlr(); > isb(); > } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel