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Tue, 27 Apr 2021 14:43:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 66ADDD6E; Tue, 27 Apr 2021 07:43:38 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.31.135]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0D9C93F73B; Tue, 27 Apr 2021 07:43:35 -0700 (PDT) Date: Tue, 27 Apr 2021 15:43:33 +0100 From: Mark Rutland To: Zenghui Yu , maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org, elver@google.com, paulmck@kernel.org, peterz@infradead.org, catalin.marinas@arm.com, james.morse@arm.com, dvyukov@google.com, wanghaibin.wang@huawei.com Subject: Re: [PATCHv2 09/11] arm64: entry: fix non-NMI kernel<->kernel transitions Message-ID: <20210427144333.GD37475@C02TD0UTHF1T.local> References: <20201130115950.22492-1-mark.rutland@arm.com> <20201130115950.22492-10-mark.rutland@arm.com> <20210426092139.GA16287@C02TD0UTHF1T.local> <0e1143a5-8e1a-c04e-e4fd-5c57f8354f61@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210427_074342_607086_669824D5 X-CRM114-Status: GOOD ( 14.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 27, 2021 at 03:15:39PM +0800, Zenghui Yu wrote: > On 2021/4/26 21:39, Zenghui Yu wrote: > > Hi Mark, > > > > On 2021/4/26 17:21, Mark Rutland wrote: > > > > > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > > > index 6acfc5e6b5e0..7d46c74a8706 100644 > > > --- a/arch/arm64/kernel/entry.S > > > +++ b/arch/arm64/kernel/entry.S > > > @@ -292,6 +292,8 @@ alternative_else_nop_endif > > > alternative_if ARM64_HAS_IRQ_PRIO_MASKING > > > mrs_s x20, SYS_ICC_PMR_EL1 > > > str x20, [sp, #S_PMR_SAVE] > > > + orr x20, x20, #GIC_PRIO_PSR_I_SET > > > + msr_s SYS_ICC_PMR_EL1, x20 > > > alternative_else_nop_endif > > > > While this does fix the lockdep part, it breaks something else. The > > sleep-in-atomic one stands out (which says, I've seen other splats > > triggered with this diff), where irqs_disabled() in do_mem_abort() now > > gets confused by the updated PMR (GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET). > > Seem that this can be addressed by restoring pt_regs->pmr_save into PMR > in local_daif_inherit() (before we restore the DAIF bits)? I think so, yes. Looking at this some more, I'm not sure whether the entry code should: * ORR in GIC_PRIO_PSR_I_SET, matching gic_prio_irq_setup * MOV in (GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET) matching gic_prio_kentry_setup ... as it's not clear to me why the two differ, nor whether we can follow the same approach in both cases. I'll dig a bit more through the history and see what I can dredge up, unless Marc has any ideas. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel