[RFC 0/4] soc: imx8mn: Add additional power domains

[RFC 0/4] soc: imx8mn: Add additional power domains

[Adam Ford]

The i.MX8M Nano is similar to the i.MX8M Mini is some ways, but there
are enough differences that require the Nano to have its own
power domains in both gpcv2 and blk-ctl.

This series is based on a few series
[1] - from Peng and Lucas which updates the GPCv2
[2] - from Peng which adds the blk-ctl
[3] - from myself which adds imx8mn to the GPCv2

[1] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210506010440.7016-2-peng.fan@oss.nxp.com/
[2] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210506041555.10719-2-peng.fan@oss.nxp.com/
[3] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210429211625.1835702-6-aford173@gmail.com/


Adam Ford (4):
  soc: imx: gpcv2: add support for i.MX8MN power domains
  Documentation: bindings: fsl,imx-blk-ctl: Support imx8mn
  soc: imx: Add blk-ctl driver for i.MX8MN
  arm64: dts: imx8mn:  Enable blt-ctl power domains

 .../bindings/soc/imx/fsl,imx-blk-ctl.yaml     |   1 +
 arch/arm64/boot/dts/freescale/imx8mn.dtsi     |  35 ++++++
 drivers/soc/imx/Makefile                      |   2 +-
 drivers/soc/imx/blk-ctl-imx8mn.c              | 118 ++++++++++++++++++
 drivers/soc/imx/gpcv2.c                       |  93 ++++++++++++++
 include/dt-bindings/power/imx8mn-power.h      |  21 ++++
 6 files changed, 269 insertions(+), 1 deletion(-)
 create mode 100644 drivers/soc/imx/blk-ctl-imx8mn.c
 create mode 100644 include/dt-bindings/power/imx8mn-power.h

-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[RFC 1/4] soc: imx: gpcv2: add support for i.MX8MN power domains

[Adam Ford]

This adds support for the power domains founds on i.MX8MN. The Nano
has fewer domains than the Mini, and the access to some of these domains
is different than that of the Mini, the Mini power domains cannot be
reused.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 35bbb1bc5159..3120718e1dd7 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -20,6 +20,7 @@
 #include <dt-bindings/power/imx7-power.h>
 #include <dt-bindings/power/imx8mq-power.h>
 #include <dt-bindings/power/imx8mm-power.h>
+#include <dt-bindings/power/imx8mn-power.h>
 
 #define GPC_LPCR_A_CORE_BSC			0x000
 
@@ -58,6 +59,12 @@
 #define IMX8MM_PCIE_A53_DOMAIN			BIT(3)
 #define IMX8MM_MIPI_A53_DOMAIN			BIT(2)
 
+#define IMX8MN_DISPMIX_A53_DOMAIN		BIT(12)
+#define IMX8MN_GPUMIX_A53_DOMAIN		BIT(9)
+#define IMX8MN_DDR1_A53_DOMAIN		BIT(7)
+#define IMX8MN_OTG1_A53_DOMAIN		BIT(4)
+#define IMX8MN_MIPI_A53_DOMAIN		BIT(2)
+
 #define GPC_PU_PGC_SW_PUP_REQ		0x0f8
 #define GPC_PU_PGC_SW_PDN_REQ		0x104
 
@@ -94,6 +101,12 @@
 #define IMX8MM_PCIE_SW_Pxx_REQ			BIT(1)
 #define IMX8MM_MIPI_SW_Pxx_REQ			BIT(0)
 
+#define IMX8MN_DISPMIX_SW_Pxx_REQ		BIT(10)
+#define IMX8MN_GPUMIX_SW_Pxx_REQ		BIT(7)
+#define IMX8MN_DDR1_SW_Pxx_REQ		BIT(5)
+#define IMX8MN_OTG1_SW_Pxx_REQ		BIT(2)
+#define IMX8MN_MIPI_SW_Pxx_REQ		BIT(0)
+
 #define GPC_M4_PU_PDN_FLG		0x1bc
 
 #define GPC_PU_PWRHSK			0x1fc
@@ -116,6 +129,14 @@
 #define IMX8MM_VPUMIX_HSK_PWRDNREQN		BIT(8)
 #define IMX8MM_DISPMIX_HSK_PWRDNREQN		BIT(7)
 #define IMX8MM_HSIO_HSK_PWRDNREQN		(BIT(5) | BIT(6))
+
+#define IMX8MN_GPUMIX_HSK_PWRDNACKN		(BIT(29) | BIT(27))
+#define IMX8MN_DISPMIX_HSK_PWRDNACKN		BIT(25)
+#define IMX8MN_HSIO_HSK_PWRDNACKN		BIT(23)
+#define IMX8MN_GPUMIX_HSK_PWRDNREQN		(BIT(11) | BIT(9))
+#define IMX8MN_DISPMIX_HSK_PWRDNREQN		BIT(7)
+#define IMX8MN_HSIO_HSK_PWRDNREQN		BIT(5)
+
 /*
  * The PGC offset values in Reference Manual
  * (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -152,6 +173,12 @@
 #define IMX8MM_PGC_VPUG2		28
 #define IMX8MM_PGC_VPUH1		29
 
+#define IMX8MN_PGC_MIPI		16
+#define IMX8MN_PGC_OTG1		18
+#define IMX8MN_PGC_DDR1		21
+#define IMX8MN_PGC_GPUMIX		23
+#define IMX8MN_PGC_DISPMIX		26
+
 #define GPC_PGC_CTRL(n)			(0x800 + (n) * 0x40)
 #define GPC_PGC_SR(n)			(GPC_PGC_CTRL(n) + 0xc)
 
@@ -764,6 +791,71 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
 	.reg_access_table = &imx8mm_access_table,
 };
 
+static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
+	[IMX8MN_POWER_DOMAIN_HSIOMIX] = {
+		.genpd = {
+			.name = "hsiomix",
+		},
+		.bits  = {
+			.pxx = 0, /* no power sequence control */
+			.map = 0, /* no power sequence control */
+			.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
+			.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
+		},
+	},
+
+	[IMX8MN_POWER_DOMAIN_OTG1] = {
+		.genpd = {
+			.name = "usb-otg1",
+		},
+		.bits  = {
+			.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
+			.map = IMX8MN_OTG1_A53_DOMAIN,
+		},
+		.pgc   = IMX8MN_PGC_OTG1,
+	},
+
+	[IMX8MN_POWER_DOMAIN_GPUMIX] = {
+		.genpd = {
+			.name = "gpumix",
+		},
+		.bits  = {
+			.pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
+			.map = IMX8MN_GPUMIX_A53_DOMAIN,
+			.hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
+			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
+		},
+		.pgc   = IMX8MN_PGC_GPUMIX,
+	},
+};
+
+static const struct regmap_range imx8mn_yes_ranges[] = {
+	regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+			 GPC_PU_PWRHSK),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
+			 GPC_PGC_SR(IMX8MN_PGC_MIPI)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
+			 GPC_PGC_SR(IMX8MN_PGC_OTG1)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
+			 GPC_PGC_SR(IMX8MN_PGC_DDR1)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
+			 GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
+			 GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
+};
+
+static const struct regmap_access_table imx8mn_access_table = {
+	.yes_ranges	= imx8mn_yes_ranges,
+	.n_yes_ranges	= ARRAY_SIZE(imx8mn_yes_ranges),
+};
+
+static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
+	.domains = imx8mn_pgc_domains,
+	.domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
+	.reg_access_table = &imx8mn_access_table,
+};
+
+
 static int imx_pgc_domain_probe(struct platform_device *pdev)
 {
 	struct imx_pgc_domain *domain = pdev->dev.platform_data;
@@ -948,6 +1040,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
 static const struct of_device_id imx_gpcv2_dt_ids[] = {
 	{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
 	{ .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
+	{ .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
 	{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
 	{ }
 };
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[RFC 2/4] Documentation: bindings: fsl,imx-blk-ctl: Support imx8mn

[Adam Ford]

The imx8mn has a similar dispmix to that of the imx8mm, however
there are some additionl power domains that will be needed
for additional peripherals that were not present on the imx8mm,
so it needs a unique blk-ctl.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
index a66f11acc6b4..da1951bf6d27 100644
--- a/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
@@ -23,6 +23,7 @@ properties:
       - enum:
           - fsl,imx8mm-dispmix-blk-ctl
           - fsl,imx8mm-vpumix-blk-ctl
+          - fsl,imx8mn-dispmix-blk-ctl
       - const: syscon
 
   reg:
diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h
new file mode 100644
index 000000000000..3817fcfcc565
--- /dev/null
+++ b/include/dt-bindings/power/imx8mn-power.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ *  Copyright (C) 2020 Compass Electronics Group, LLC
+ */
+
+#ifndef __DT_BINDINGS_IMX8MN_POWER_H__
+#define __DT_BINDINGS_IMX8MN_POWER_H__
+
+#define IMX8MN_POWER_DOMAIN_HSIOMIX	0
+#define IMX8MN_POWER_DOMAIN_OTG1	1
+#define IMX8MN_POWER_DOMAIN_GPUMIX	2
+#define IMX8MN_POWER_DOMAIN_DISPMIX	3
+#define IMX8MN_POWER_DOMAIN_MIPI	4
+
+#define IMX8MN_BLK_CTL_DISPMIX_ISI		0
+#define IMX8MN_BLK_CTL_DISPMIX_LCDIF		1
+#define IMX8MN_BLK_CTL_DISPMIX_MIPI_DSI	2
+#define IMX8MN_BLK_CTL_DISPMIX_MIPI_CSI	3
+#define IMX8MN_BLK_CTL_DISPMIX_MAX_PD		4
+
+#endif
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[RFC 3/4] soc: imx: Add blk-ctl driver for i.MX8MN

[Adam Ford]

The i.MX8MN SoC has dispmix BLK-CTL. It's similar to the
i.MX8MM, but there are subtle differences, so it needs its own.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index c260b962f495..3bcd7d5fd7ed 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -4,4 +4,4 @@ obj-$(CONFIG_ARCH_MXC) += soc-imx.o
 endif
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
-obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o blk-ctl.o blk-ctl-imx8mm.o
+obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o blk-ctl.o blk-ctl-imx8mm.o blk-ctl-imx8mn.o
diff --git a/drivers/soc/imx/blk-ctl-imx8mn.c b/drivers/soc/imx/blk-ctl-imx8mn.c
new file mode 100644
index 000000000000..eeb5c82bcf9a
--- /dev/null
+++ b/drivers/soc/imx/blk-ctl-imx8mn.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <dt-bindings/clock/imx8mn-clock.h>
+#include <dt-bindings/power/imx8mn-power.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/pm_domain.h>
+#include <linux/regmap.h>
+
+#include "blk-ctl.h"
+
+#define MEDIA_BLK_SFT_EN_BUS_CLK_RSTN				BIT(8)
+#define MEDIA_BLK_SFT_EN_ISI_CLK_RSTN				GENMASK(7, 6)
+#define MEDIA_BLK_SFT_EN_LCDIF_CLK_RSTN			GENMASK(5, 4)
+#define MEDIA_BLK_SFT_EN_MIPI_CSI_RSTN			GENMASK(3, 2)
+#define MEDIA_BLK_SFT_EN_DSI_RSTN				GENMASK(1, 0)
+
+#define MEDIA_BLK_BUS_PD_MASK					BIT(8)
+#define MEDIA_BLK_ISI_PD_MASK					GENMASK(7,6)
+#define MEDIA_BLK_LCDIF_PD_MASK				GENMASK(5, 4)
+#define MEDIA_BLK_MIPI_CSI_PD_MASK				GENMASK(3, 2)
+#define MEDIA_BLK_MIPI_DSI_PD_MASK				GENMASK(1, 0)
+
+static struct imx_blk_ctl_hw imx8mn_dispmix_blk_ctl_pds[] = {
+	IMX_BLK_CTL_PD("ISI", "dispmix", IMX8MN_BLK_CTL_DISPMIX_ISI, 0x4,
+		       MEDIA_BLK_ISI_PD_MASK, 0, MEDIA_BLK_SFT_EN_ISI_CLK_RSTN,
+		       IMX_BLK_CTL_PD_RESET),
+	IMX_BLK_CTL_PD("LCDIF", "dispmix", IMX8MN_BLK_CTL_DISPMIX_LCDIF, 0x4,
+		       MEDIA_BLK_LCDIF_PD_MASK, 0, MEDIA_BLK_SFT_EN_LCDIF_CLK_RSTN,
+		       IMX_BLK_CTL_PD_RESET),
+	IMX_BLK_CTL_PD("MIPI_DSI", "dispmix", IMX8MN_BLK_CTL_DISPMIX_MIPI_DSI, 0x4,
+		       MEDIA_BLK_MIPI_DSI_PD_MASK, 0, MEDIA_BLK_SFT_EN_DSI_RSTN,
+		       IMX_BLK_CTL_PD_RESET),
+	IMX_BLK_CTL_PD("MIPI_CSI", "ISI", IMX8MN_BLK_CTL_DISPMIX_MIPI_CSI, 0x4,
+		       MEDIA_BLK_MIPI_CSI_PD_MASK, 0, MEDIA_BLK_SFT_EN_MIPI_CSI_RSTN,
+		       IMX_BLK_CTL_PD_RESET),
+};
+
+static const struct regmap_config imx8mn_blk_ctl_regmap_config = {
+	.reg_bits		= 32,
+	.reg_stride		= 4,
+	.val_bits		= 32,
+	.max_register		= 0x30,
+	.fast_io		= true,
+};
+
+static const struct imx_blk_ctl_dev_data imx8mn_dispmix_blk_ctl_dev_data = {
+	.pds = imx8mn_dispmix_blk_ctl_pds,
+	.pds_num = ARRAY_SIZE(imx8mn_dispmix_blk_ctl_pds),
+	.hw_hsk = IMX_BLK_CTL_PD(NULL, NULL, -1, 0x4, MEDIA_BLK_BUS_PD_MASK, 0,
+				 MEDIA_BLK_SFT_EN_BUS_CLK_RSTN,
+				 IMX_BLK_CTL_PD_HANDSHAKE | IMX_BLK_CTL_PD_RESET),
+	.config = imx8mn_blk_ctl_regmap_config,
+	.active_pd_names = (char*[]){"dispmix", "mipi"},
+	.num_active_pd = 2,
+};
+
+static int imx8mn_blk_ctl_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev);
+	struct regmap *regmap;
+	struct imx_blk_ctl *ctl;
+	void __iomem *base;
+
+	ctl = devm_kzalloc(dev, sizeof(*ctl), GFP_KERNEL);
+	if (!ctl)
+		return -ENOMEM;
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	regmap = devm_regmap_init_mmio(dev, base, &dev_data->config);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	ctl->regmap = regmap;
+	ctl->dev = dev;
+	ctl->power_count = 0;
+	mutex_init(&ctl->lock);
+
+	ctl->num_clks = devm_clk_bulk_get_all(dev, &ctl->clks);
+	if (ctl->num_clks < 0)
+		return ctl->num_clks;
+
+	dev_set_drvdata(dev, ctl);
+	ctl->dev_data = dev_data;
+
+	return imx_blk_ctl_register(dev);
+}
+
+static const struct of_device_id imx_blk_ctl_of_match[] = {
+	{ .compatible = "fsl,imx8mn-dispmix-blk-ctl", .data = &imx8mn_dispmix_blk_ctl_dev_data },
+	{ /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_blk_ctl_of_match);
+
+static struct platform_driver imx_blk_ctl_driver = {
+	.probe = imx8mn_blk_ctl_probe,
+	.driver = {
+		.name = "imx8mn-blk-ctl",
+		.of_match_table = of_match_ptr(imx_blk_ctl_of_match),
+		.pm = &imx_blk_ctl_pm_ops,
+	},
+};
+module_platform_driver(imx_blk_ctl_driver);
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[RFC 4/4] arm64: dts: imx8mn: Enable blt-ctl power domains

[Adam Ford]

There are a few blk-ctl power domains required for peripherals
like ISI, CSI, DSI, and LCDIF.  These new power domains require
dispmix, and mipi from the gpcv2 controller in order to operate.
Add them all.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
Note: This series is an RFC because the 8MN hangs when resuming
from suspend, and I am looking for suggestions and feedback

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 7f8e7e24dadf..d7d91fb9b7b6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -646,6 +646,29 @@ pgc_gpumix: power-domain@2 {
 							 <&clk IMX8MN_CLK_GPU_AHB>;
 						resets = <&src IMX8MQ_RESET_GPU_RESET>;
 					};
+					
+					pgc_dispmix: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
+						clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+							 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+							 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+						assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>,
+								  <&clk IMX8MN_CLK_DISP_AXI>,
+								  <&clk IMX8MN_CLK_DISP_APB>;
+						assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>,
+									  <&clk IMX8MN_SYS_PLL2_1000M>,
+									  <&clk IMX8MN_SYS_PLL1_800M>;
+						assigned-clock-rate = <594000000>,
+									<500000000>,
+									<200000000>;
+                                       };
+
+                                       pgc_mipi: power-domain@4 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MN_POWER_DOMAIN_MIPI>;
+                                               power-domains = <&pgc_dispmix>;
+                                       };
 				};
 			};
 		};
@@ -990,6 +1013,18 @@ aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges;
 
+			dispmix_blk_ctl: blk-ctl@32e28000 {
+				compatible = "fsl,imx8mn-dispmix-blk-ctl", "syscon";
+				reg = <0x32e28000 0x100>;
+				#power-domain-cells = <1>;
+				power-domains = <&pgc_dispmix>, <&pgc_mipi>;
+				power-domain-names = "dispmix", "mipi";
+				clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+				clock-names = "disp", "axi", "apb";
+			};
+
 			usbotg1: usb@32e40000 {
 				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
 				reg = <0x32e40000 0x200>;
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel