From: Mark Brown <broonie@kernel.org>
To: Dave Martin <Dave.Martin@arm.com>
Cc: Catalin Marinas <Catalin.Marinas@arm.com>,
Will Deacon <will@kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v1 1/3] arm64/sve: Split _sve_flush macro into separate Z, P and FFR flushes
Date: Mon, 10 May 2021 17:19:58 +0100 [thread overview]
Message-ID: <20210510161958.GD4496@sirena.org.uk> (raw)
In-Reply-To: <20210510153159.GA4187@arm.com>
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On Mon, May 10, 2021 at 04:47:23PM +0100, Dave Martin wrote:
> On Mon, May 10, 2021 at 04:22:53PM +0100, Mark Brown wrote:
> > On Mon, May 10, 2021 at 03:57:11PM +0100, Dave P Martin wrote:
> > > If not, can we keep these combined? We could either keep the name
> > > sve_flush_p (since the FFR is a predicate register, if a weird kind of
> > > one), or go with something more descriptive such as sve_flush_p_and_ffr.
> > Not right now but I do expect to build on this in the not too distant
> > future.
> OK, but due to the fact that we need to dirty a P-register in order to
> zero the FFR, these still don't feel like independent operations.
Indeed, like I said I got confused by the way the macros end up being
written when I originally wrote this.
> Can we control the clearing of the FFR (or not) with an argument to a
> combined macro?
It's an option, I'm poking around with how to do it.
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next prev parent reply other threads:[~2021-05-10 16:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-10 12:23 [PATCH v1 0/3] arm64/sve: Trivial optimisation for 128 bit SVE vectors Mark Brown
2021-05-10 12:23 ` [PATCH v1 1/3] arm64/sve: Split _sve_flush macro into separate Z, P and FFR flushes Mark Brown
2021-05-10 14:57 ` Dave P Martin
2021-05-10 15:22 ` Mark Brown
2021-05-10 15:47 ` Dave Martin
2021-05-10 16:19 ` Mark Brown [this message]
2021-05-11 12:28 ` Dave Martin
2021-05-10 12:23 ` [PATCH v1 2/3] arm64/sve: Use the sve_flush macros in sve_load_from_fpsimd_state() Mark Brown
2021-05-10 12:23 ` [PATCH v1 3/3] arm64/sve: Skip flushing Z registers with 128 bit vectors Mark Brown
2021-05-10 15:08 ` Dave P Martin
2021-05-10 16:16 ` Mark Brown
2021-05-11 12:39 ` Dave Martin
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