From: Nishanth Menon <nm@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Lokesh Vutla <lokeshvutla@ti.com>, <a-govindraju@ti.com>
Subject: Re: [PATCH 4/5] arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port
Date: Wed, 12 May 2021 14:40:22 -0500 [thread overview]
Message-ID: <20210512194022.27h53llpxmvg3eoe@splurge> (raw)
In-Reply-To: <20210512150107.26793-5-kishon@ti.com>
On 20:31-20210512, Kishon Vijay Abraham I wrote:
> Enable USB Super-Speed HOST port.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 39 ++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> index 8424cd071955..056c1b2df559 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> @@ -5,6 +5,8 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/mux/ti-serdes.h>
> +#include <dt-bindings/phy/phy.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/net/ti-dp83867.h>
> #include "k3-am642.dtsi"
> @@ -85,6 +87,12 @@
> >;
> };
>
> + main_usb0_pins_default: main-usb0-pins-default {
> + pinctrl-single,pins = <
> + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
> + >;
> + };
> +
> main_i2c1_pins_default: main-i2c1-pins-default {
> pinctrl-single,pins = <
> AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
> @@ -235,6 +243,37 @@
> disable-wp;
> };
>
> +&serdes_ln_ctrl {
> + idle-states = <AM64_SERDES0_LANE0_USB>;
> +};
> +
> +&serdes_wiz0 {
> + status = "okay";
not sure I understand why default of okay needs to be explicitly stated
as okay in board dts.
> +};
> +
> +&serdes0 {
> + serdes0_usb_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <1>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_USB3>;
> + resets = <&serdes_wiz0 1>;
> + };
> +};
> +
> +&usbss0 {
> + ti,vbus-divider;
> +};
> +
> +&usb0 {
> + dr_mode = "host";
> + maximum-speed = "super-speed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_usb0_pins_default>;
> + phys = <&serdes0_usb_link>;
> + phy-names = "cdns3,usb3-phy";
> +};
> +
> &cpsw3g {
> pinctrl-names = "default";
> pinctrl-0 = <&mdio1_pins_default
> --
> 2.17.1
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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next prev parent reply other threads:[~2021-05-12 19:45 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-12 15:01 [PATCH 0/5] AM64: EVM/SK: Enable PCIe and USB Kishon Vijay Abraham I
2021-05-12 15:01 ` [PATCH 1/5] arm64: dts: ti: k3-am64-main: Add SERDES DT node Kishon Vijay Abraham I
2021-05-12 15:01 ` [PATCH 2/5] arm64: dts: ti: k3-am64-main: Add PCIe " Kishon Vijay Abraham I
2021-05-12 15:01 ` [PATCH 3/5] arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES Kishon Vijay Abraham I
2021-05-12 15:01 ` [PATCH 4/5] arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port Kishon Vijay Abraham I
2021-05-12 19:40 ` Nishanth Menon [this message]
2021-05-13 12:35 ` Kishon Vijay Abraham I
2021-05-12 15:01 ` [PATCH 5/5] arm64: dts: ti: k3-am642-sk: Disable PCIe Kishon Vijay Abraham I
2021-05-12 18:46 ` [PATCH 0/5] AM64: EVM/SK: Enable PCIe and USB Nishanth Menon
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