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From: Catalin Marinas <catalin.marinas@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>, Dave Martin <Dave.Martin@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 0/3] arm64/sve: Trivial optimisation for 128 bit SVE vectors
Date: Fri, 14 May 2021 12:03:22 +0100	[thread overview]
Message-ID: <20210514110321.GE855@arm.com> (raw)
In-Reply-To: <20210512151131.27877-1-broonie@kernel.org>

On Wed, May 12, 2021 at 04:11:28PM +0100, Mark Brown wrote:
> This series is a combination of factoring out some duplicated code and a
> very minor optimisation to the performance of handling converting FPSIMD
> state to SVE in the live registers for 128 bit SVE vectors.
> 
> v3:
>  - Tweak comment.
> v2:
>  - Combine P and FFR flushing into a single macro.
> 
> Mark Brown (3):
>   arm64/sve: Split _sve_flush macro into separate Z and predicate
>     flushes
>   arm64/sve: Use the sve_flush macros in sve_load_from_fpsimd_state()
>   arm64/sve: Skip flushing Z registers with 128 bit vectors

I acked v2, hadn't noticed v3 was out. So here it is again:

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

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  parent reply	other threads:[~2021-05-14 11:04 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-12 15:11 Mark Brown
2021-05-12 15:11 ` [PATCH v3 1/3] arm64/sve: Split _sve_flush macro into separate Z and predicate flushes Mark Brown
2021-05-12 15:11 ` [PATCH v3 2/3] arm64/sve: Use the sve_flush macros in sve_load_from_fpsimd_state() Mark Brown
2021-05-12 15:11 ` [PATCH v3 3/3] arm64/sve: Skip flushing Z registers with 128 bit vectors Mark Brown
2021-05-14 11:03 ` Catalin Marinas [this message]
2021-05-26 22:15 ` [PATCH v3 0/3] arm64/sve: Trivial optimisation for 128 bit SVE vectors Will Deacon

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