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Mon, 17 May 2021 13:36:57 GMT Received: from pps.reinject (localhost [127.0.0.1]) by userp3030.oracle.com with ESMTP id 38j3dtbgse-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 17 May 2021 13:36:57 +0000 Received: from userp3030.oracle.com (userp3030.oracle.com [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 14HDXrvv120420; Mon, 17 May 2021 13:36:56 GMT Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by userp3030.oracle.com with ESMTP id 38j3dtbgrw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 17 May 2021 13:36:56 +0000 Received: from abhmp0007.oracle.com (abhmp0007.oracle.com [141.146.116.13]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id 14HDaqhO028744; Mon, 17 May 2021 13:36:52 GMT Received: from kadam (/102.36.221.92) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Mon, 17 May 2021 06:36:51 -0700 Date: Mon, 17 May 2021 16:36:43 +0300 From: Dan Carpenter To: Andy Shevchenko Cc: Colin King , Shubhrajyoti Datta , Srinivas Neeli , Michal Simek , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , "open list:GPIO SUBSYSTEM" , linux-arm Mailing List , kernel-janitors , Linux Kernel Mailing List Subject: Re: [PATCH][next] gpio: xilinx: Fix potential integer overflow on shift of a u32 int Message-ID: <20210517133643.GI1955@kadam> References: <20210513085227.54392-1-colin.king@canonical.com> <20210514053754.GZ1955@kadam> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-Proofpoint-GUID: dLB8ec6Q_IuAwH4IsNLDCEHIoe1f52oG X-Proofpoint-ORIG-GUID: dLB8ec6Q_IuAwH4IsNLDCEHIoe1f52oG X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210517_063705_337744_7A65AF8E X-CRM114-Status: GOOD ( 26.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, May 17, 2021 at 10:07:20AM +0300, Andy Shevchenko wrote: > On Fri, May 14, 2021 at 12:26 PM Dan Carpenter wrote: > > On Thu, May 13, 2021 at 09:52:27AM +0100, Colin King wrote: > > ... > > > > const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); > > > > > > map[index] &= ~(0xFFFFFFFFul << offset); > > > - map[index] |= v << offset; > > > + map[index] |= (unsigned long)v << offset; > > > > Doing a shift by BIT(5) is super weird. > > Not the first place in the kernel with such a trick. > > > It looks like a double shift > > bug and should probably trigger a static checker warning. It's like > > when people do BIT(BIT(5)). > > > > It would be more readable to write it as: > > > > int shift = (bit % BITS_PER_LONG) ? 32 : 0; > > Usually this code is in a kinda fast path. Have you checked if the > compiler generates the same or better code when you are using ternary? I wrote a little benchmark to see which was faster and they're the same as far as I can see. regards, dan carpenter static inline __attribute__((__gnu_inline__)) unsigned long xgpio_set_value_orig(unsigned long *map, int bit, u32 v) { int shift = (bit % 64) & ((((1UL))) << (5)); return v << shift; } static inline __attribute__((__gnu_inline__)) unsigned long xgpio_set_value_new(unsigned long *map, int bit, u32 v) { int shift = (bit % 64) ? 32 : 0; return v << shift; } int main(void) { int i; for (i = 0; i < INT_MAX; i++) xgpio_set_value_orig(NULL, i, 0); // for (i = 0; i < INT_MAX; i++) // xgpio_set_value_new(NULL, i, 0); return 0; } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel