From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-22.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE0DDC433ED for ; Mon, 17 May 2021 19:57:17 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6EE3F60FF3 for ; Mon, 17 May 2021 19:57:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6EE3F60FF3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Xngkz8arArfGHYwSKJ5p4hjUUBf3wqtkEvxmFxsYBOk=; b=p5w3z7K42M0649SjcLWw3TgQZ 6u4TNOnPpybWTx3vTRlXa/MP6J4JCdcclzezFLS9yIdcXxnjLCIw2Jzmsyv6Qi4iq8Ojtf80w6+7J A7swULye29BGqtlMfzZBsnVjkOnig1BfY7Fv2be/aDVEzJeLrAtW/OCNilOfCCd5f5NVhP33Cvx1w 1qr+6WAANQHq4tjAYXbj8y04WbB1Cn0R8kLTVmRW+V1TcAWv9tMfvtsiXfh6iHAEiV1brFnpPHM60 FQfPGUOHHQIeq1XVPOPCR3FYKwfsSm6LKiZR9O8JyajeDiwQdBctiiZ+bIcYhKuC4l0gnGk+rDpMi zGBT2cZ1Q==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lijKl-00FzVI-GQ; Mon, 17 May 2021 19:55:23 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lijJl-00FzHG-MD for linux-arm-kernel@desiato.infradead.org; Mon, 17 May 2021 19:54:21 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=ox5Uad03HIvUneUEV0ZALlKBmbYKT82BLfWq3q/UJso=; b=cvA3OMw+TkyU1mVZboWuaq1hxM esnl0DyGpCuvfw8NRJgT6XA7lkVtExE8HobD+DKZIAdwOtMKIKcmLV+AkIJvnkjHp58I/uU9uBsa8 O3UmLi5uR5QMB4Mov7FsMCKvxeqiVC0PSf5dr0mVO3C/WJtLODZJonVmpJy0i1GUDUVQqTgMteQ8t PJysAAZdknQWtQ8+PRnBTvRojvskc8tBT8GG6xVe/Y4agT3jocYShhyV9gc17CmCa/mIy0d4WJAiV 30uScL+Jt9tUr7d2Bsp8uD10X1lEUE1Uoea0V13W2RS50b4OlYCWqqDGLcIw2dudjbcNLYl6SEpnP RKXTEhQA==; Received: from mail-ot1-f54.google.com ([209.85.210.54]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lijJi-00E6bk-Qe for linux-arm-kernel@lists.infradead.org; Mon, 17 May 2021 19:54:20 +0000 Received: by mail-ot1-f54.google.com with SMTP id 36-20020a9d0ba70000b02902e0a0a8fe36so6604194oth.8 for ; Mon, 17 May 2021 12:54:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ox5Uad03HIvUneUEV0ZALlKBmbYKT82BLfWq3q/UJso=; b=k3Gmky7CmUv6vRiLwN8/8gNV4qsRYq4K1NTsXf0busTTfxc0DElnVt/y+kt8XYqOu7 IPNlSvrWbZ7kvqAJ4z3wrfJaYxECau+3urAkgzrhgisMUjLC7qq0oTcLp+0IWTSHCl+/ 2GXn/Qix4ZARvhWhMcH8nUY1aLD1HR+MqBL2pN+y/OTsXsZgp1r0PQVf/1h+FqBhgMyn Ki3Cr2hG/PaJavsvQvFXFHRLBE0Cwk7f1K3Qkng7JTrap1GefZRT55ARgeGu6TPbrwFM +CqCTy3ofyEFcnLUp1IwTwc3XFkTShiwkh4ztny4z/j9LjN0jBLyNvs85ZVUjgmMv9BP 01eQ== X-Gm-Message-State: AOAM5303cbRzS47N9E8TxVCamH9FAoc8OXu8j6wyXp0WzV45c5rfYOgr DwmnL1wezJSkilqOfzqB2Q== X-Google-Smtp-Source: ABdhPJxA55TueFl6ZH0b8jUa6655l5IlMrQ6hNVNItlskSFPY1EzoUbAAg7NtPBD/z5noHYY2Xiaqg== X-Received: by 2002:a9d:6244:: with SMTP id i4mr1019131otk.182.1621281257538; Mon, 17 May 2021 12:54:17 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id m81sm2920758oig.43.2021.05.17.12.54.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 12:54:16 -0700 (PDT) From: Rob Herring To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Mark Rutland Cc: Arnaldo Carvalho de Melo , Jiri Olsa , Kan Liang , Ian Rogers , Alexander Shishkin , honnappa.nagarahalli@arm.com, Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 5/5] Documentation: arm64: Document PMU counters access from userspace Date: Mon, 17 May 2021 14:54:05 -0500 Message-Id: <20210517195405.3079458-6-robh@kernel.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210517195405.3079458-1-robh@kernel.org> References: <20210517195405.3079458-1-robh@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210517_125418_890360_AB05F4BF X-CRM114-Status: GOOD ( 23.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Raphael Gault Add documentation to describe the access to the pmu hardware counters from userspace. Signed-off-by: Raphael Gault Signed-off-by: Rob Herring --- v8: - Reword that config1:1 must always be set to request user access v7: - Merge into existing arm64 perf.rst v6: - Update the chained event section with attr.config1 details v2: - Update links to test examples Changes from Raphael's v4: - Convert to rSt - Update chained event status - Add section for heterogeneous systems --- Documentation/arm64/perf.rst | 68 +++++++++++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/perf.rst b/Documentation/arm64/perf.rst index b567f177d385..5dcbb508586f 100644 --- a/Documentation/arm64/perf.rst +++ b/Documentation/arm64/perf.rst @@ -2,7 +2,10 @@ .. _perf_index: -===================== +==== +Perf +==== + Perf Event Attributes ===================== @@ -88,3 +91,66 @@ exclude_host. However when using !exclude_hv there is a small blackout window at the guest entry/exit where host events are not captured. On VHE systems there are no blackout windows. + +Perf Userspace PMU Hardware Counter Access +========================================== + +Overview +-------- +The perf userspace tool relies on the PMU to monitor events. It offers an +abstraction layer over the hardware counters since the underlying +implementation is cpu-dependent. +Arm64 allows userspace tools to have access to the registers storing the +hardware counters' values directly. + +This targets specifically self-monitoring tasks in order to reduce the overhead +by directly accessing the registers without having to go through the kernel. + +How-to +------ +The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu +registers is enabled and that the userspace has access to the relevant +information in order to use them. + +In order to have access to the hardware counter it is necessary to open the +event using the perf tool interface with config1:1 attr bit set: the +sys_perf_event_open syscall returns a fd which can subsequently be used +with the mmap syscall in order to retrieve a page of memory containing +information about the event. The PMU driver uses this page to expose to +the user the hardware counter's index and other necessary data. Using +this index enables the user to access the PMU registers using the `mrs` +instruction. + +The userspace access is supported in libperf using the perf_evsel__mmap() +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for +an example. + +About heterogeneous systems +--------------------------- +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can +only be enabled when the tasks are pinned to a homogeneous subset of cores and +the corresponding PMU instance is opened by specifying the 'type' attribute. +The use of generic event types is not supported in this case. + +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It +can be run using the perf tool to check that the access to the registers works +correctly from userspace: + +.. code-block:: sh + + perf test -v user + +About chained events and 64-bit counters +---------------------------------------- +Chained events are not supported in conjunction with userspace counter +access. If a 64-bit counter is requested (attr.config1:0) with userspace +access (attr.config1:1 set), then counter chaining will be disabled. The +'pmc_width' in the user page will indicate the actual width of the +counter which could be only 32-bits depending on the event and PMU +features. + +.. Links +.. _tools/perf/arch/arm64/tests/user-events.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c +.. _tools/lib/perf/tests/test-evsel.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel