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Tue, 18 May 2021 15:53:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E36FC6D; Tue, 18 May 2021 08:53:46 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.6.226]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 39FC83F73B; Tue, 18 May 2021 08:53:45 -0700 (PDT) Date: Tue, 18 May 2021 16:53:42 +0100 From: Mark Rutland To: Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, ardb@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, robin.murphy@arm.com Subject: Re: [PATCH v2 04/16] arm64: Downgrade flush_icache_range to invalidate Message-ID: <20210518155342.GL82842@C02TD0UTHF1T.local> References: <20210517075124.152151-1-tabba@google.com> <20210517075124.152151-5-tabba@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210517075124.152151-5-tabba@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210518_085348_438660_8DB1BFB6 X-CRM114-Status: GOOD ( 21.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, May 17, 2021 at 08:51:12AM +0100, Fuad Tabba wrote: > Since __flush_dcache_area is called right before, > invalidate_icache_range is sufficient in this case. > > Rewrite the comment to better explain the rationale behind the > cache maintenance operations used here. > > No functional change intended. > Possible performance impact due to invalidating only the icache > rather than invalidating and cleaning both caches. > > Reported-by: Catalin Marinas > Reported-by: Will Deacon > Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/ > Signed-off-by: Fuad Tabba > --- > arch/arm64/kernel/machine_kexec.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kernel/machine_kexec.c b/arch/arm64/kernel/machine_kexec.c > index 90a335c74442..ecd8915e02e1 100644 > --- a/arch/arm64/kernel/machine_kexec.c > +++ b/arch/arm64/kernel/machine_kexec.c > @@ -68,10 +68,14 @@ int machine_kexec_post_load(struct kimage *kimage) > kimage->arch.kern_reloc = __pa(reloc_code); > kexec_image_info(kimage); > > - /* Flush the reloc_code in preparation for its execution. */ > + /* > + * For execution with the MMU off and I-cache on, reloc_code needs to be > + * cleaned to the PoC and invalidated from the I-cache. > + */ Minor nit, but the I-cache is *always* on (SCTLR.I affects the attributes used for fetches into the I-caches), so it would be slightly better to drop the "and I-cache on" words. Otherwise, this looks good to me. Mark. > __flush_dcache_area(reloc_code, arm64_relocate_new_kernel_size); > - flush_icache_range((uintptr_t)reloc_code, (uintptr_t)reloc_code + > - arm64_relocate_new_kernel_size); > + invalidate_icache_range((uintptr_t)reloc_code, > + (uintptr_t)reloc_code + > + arm64_relocate_new_kernel_size); > > return 0; > } > -- > 2.31.1.751.gd2f1c929bd-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel