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From: Mark Brown <broonie@kernel.org>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 2/2] arm64: smccc: Support SMCCC v1.3 SVE register saving hint
Date: Tue, 18 May 2021 17:55:41 +0100	[thread overview]
Message-ID: <20210518165541.GD4358@sirena.org.uk> (raw)
In-Reply-To: <20210518164302.ldogm56xvhccnyas@bogus>


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On Tue, May 18, 2021 at 05:43:02PM +0100, Sudeep Holla wrote:

> I am adding another interface that extends the input/output register set
> for v1.2 and above. I assume we may need these changes there too. I have
> cc-ed you in the updated version I just posted. The lore link is not yet
> available, so sharing the one for earlier version[1]

Thanks, should just be the same update as we do in the existing SMCCC
macro to call __smccc_sve_check from the new SMCCC_1_2 macro before we
load the registers from the looks of it.  It won't do any harm to miss
it, it's just an optimisation, and the patches probably don't even
conflict.

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      reply	other threads:[~2021-05-18 16:58 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-18 10:09 [PATCH v1 0/2] arm64: Implement SMCCC v1.3 SVE register saving hint Mark Brown
2021-05-18 10:09 ` [PATCH v1 1/2] arm64: asmlinkage: Enable use of BTI_C macro in SYM_CODE Mark Brown
2021-05-18 10:09 ` [PATCH v1 2/2] arm64: smccc: Support SMCCC v1.3 SVE register saving hint Mark Brown
2021-05-18 10:53   ` Marc Zyngier
2021-05-18 11:53     ` Mark Brown
2021-05-18 12:14       ` Marc Zyngier
2021-05-18 13:01         ` Mark Brown
2021-05-18 16:53     ` Ard Biesheuvel
2021-05-18 16:43   ` Sudeep Holla
2021-05-18 16:55     ` Mark Brown [this message]

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