linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: Andre Przywara <andre.przywara@arm.com>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Rob Herring <robh@kernel.org>, Icenowy Zheng <icenowy@aosc.io>,
	Samuel Holland <samuel@sholland.org>,
	Ondrej Jirman <megous@megous.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-sunxi@googlegroups.com, linux-sunxi@lists.linux.dev,
	linux-kernel@vger.kernel.org,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Vinod Koul <vkoul@kernel.org>,
	linux-phy@lists.infradead.org, linux-usb@vger.kernel.org
Subject: [PATCH v6 10/17] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling
Date: Wed, 19 May 2021 11:41:45 +0100	[thread overview]
Message-ID: <20210519104152.21119-11-andre.przywara@arm.com> (raw)
In-Reply-To: <20210519104152.21119-1-andre.przywara@arm.com>

As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.

While we are at it, generalise the existing code by allowing a bitmap
of bits to clear and set, to cover newer SoCs: The A100 and H616 use a
different bit for the SIDDQ control.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/phy/allwinner/phy-sun4i-usb.c | 30 ++++++++++++---------------
 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 788dd5cdbb7d..142f4cafdc78 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -43,7 +43,7 @@
 #define REG_PHYCTL_A33			0x10
 #define REG_PHY_OTGCTL			0x20
 
-#define REG_PMU_UNK1			0x10
+#define REG_HCI_PHY_CTL			0x10
 
 #define PHYCTL_DATA			BIT(7)
 
@@ -82,6 +82,7 @@
 /* A83T specific control bits for PHY0 */
 #define PHY_CTL_VBUSVLDEXT		BIT(5)
 #define PHY_CTL_SIDDQ			BIT(3)
+#define PHY_CTL_H3_SIDDQ		BIT(1)
 
 /* A83T specific control bits for PHY2 HSIC */
 #define SUNXI_EHCI_HS_FORCE		BIT(20)
@@ -115,9 +116,9 @@ struct sun4i_usb_phy_cfg {
 	int hsic_index;
 	enum sun4i_usb_phy_type type;
 	u32 disc_thresh;
+	u32 hci_phy_ctl_clear;
 	u8 phyctl_offset;
 	bool dedicated_clocks;
-	bool enable_pmu_unk1;
 	bool phy0_dual_route;
 	int missing_phys;
 };
@@ -288,6 +289,12 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 		return ret;
 	}
 
+	if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
+		val = readl(phy->pmu + REG_HCI_PHY_CTL);
+		val &= ~data->cfg->hci_phy_ctl_clear;
+		writel(val, phy->pmu + REG_HCI_PHY_CTL);
+	}
+
 	if (data->cfg->type == sun8i_a83t_phy ||
 	    data->cfg->type == sun50i_h6_phy) {
 		if (phy->index == 0) {
@@ -297,11 +304,6 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 			writel(val, data->base + data->cfg->phyctl_offset);
 		}
 	} else {
-		if (phy->pmu && data->cfg->enable_pmu_unk1) {
-			val = readl(phy->pmu + REG_PMU_UNK1);
-			writel(val & ~2, phy->pmu + REG_PMU_UNK1);
-		}
-
 		/* Enable USB 45 Ohm resistor calibration */
 		if (phy->index == 0)
 			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
@@ -863,7 +865,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
@@ -872,7 +873,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
@@ -881,7 +881,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
@@ -890,7 +889,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
@@ -899,7 +897,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
@@ -908,7 +905,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
@@ -925,7 +921,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = true,
+	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 	.phy0_dual_route = true,
 };
 
@@ -935,7 +931,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = true,
+	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 	.phy0_dual_route = true,
 };
 
@@ -945,7 +941,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = true,
+	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 	.phy0_dual_route = true,
 };
 
@@ -955,7 +951,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = true,
+	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 	.phy0_dual_route = true,
 };
 
-- 
2.17.5


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-05-19 10:46 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-19 10:41 [PATCH v6 00/17] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara
2021-05-19 10:41 ` [PATCH v6 01/17] dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ) Andre Przywara
2021-05-21  1:39   ` Rob Herring
2021-05-22 14:46   ` Samuel Holland
2021-05-23  0:01     ` Andre Przywara
2021-05-19 10:41 ` [PATCH v6 02/17] mfd: axp20x: Allow AXP 806 chips without interrupt lines Andre Przywara
2021-05-19 15:01   ` Lee Jones
2021-05-19 10:41 ` [PATCH v6 03/17] dt-bindings: rtc: sun6i: Add H616 compatible string Andre Przywara
2021-05-21  1:39   ` Rob Herring
2021-05-21  2:37   ` Samuel Holland
2021-06-07 12:59     ` Andre Przywara
2021-06-08  4:23       ` Samuel Holland
2021-06-15 12:24         ` Andre Przywara
2021-06-16  9:07           ` Maxime Ripard
2021-06-16 11:28             ` Andre Przywara
2021-05-19 10:41 ` [PATCH v6 04/17] rtc: sun6i: Add support for linear day storage Andre Przywara
2021-05-22  7:26   ` Jernej Škrabec
2021-05-19 10:41 ` [PATCH v6 05/17] rtc: sun6i: Add Allwinner H616 support Andre Przywara
2021-05-22  7:29   ` Jernej Škrabec
2021-05-23  0:06     ` Andre Przywara
2021-05-19 10:41 ` [PATCH v6 06/17] dt-bindings: net: sun8i-emac: Add H616 compatible string Andre Przywara
2021-05-21  1:40   ` Rob Herring
2021-05-19 10:41 ` [PATCH v6 07/17] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register Andre Przywara
2021-05-19 10:41 ` [PATCH v6 08/17] dt-bindings: usb: Add H616 compatible string Andre Przywara
2021-05-21  1:40   ` Rob Herring
2021-05-19 10:41 ` [PATCH v6 09/17] dt-bindings: usb: sunxi-musb: " Andre Przywara
2021-05-21  1:40   ` Rob Herring
2021-05-19 10:41 ` Andre Przywara [this message]
2021-05-19 10:41 ` [PATCH v6 11/17] phy: sun4i-usb: Allow reset line to be shared Andre Przywara
2021-05-19 10:41 ` [PATCH v6 12/17] phy: sun4i-usb: Introduce port2 SIDDQ quirk Andre Przywara
2021-05-24 11:59   ` Maxime Ripard
2021-05-24 12:51     ` Jernej Škrabec
2021-05-25 11:29     ` Andre Przywara
2021-06-07 13:22       ` Maxime Ripard
2021-06-07 14:17         ` Andre Przywara
2021-06-07 14:26           ` [linux-sunxi] " Chen-Yu Tsai
2021-06-14  0:20             ` Andre Przywara
2021-05-19 10:41 ` [PATCH v6 13/17] phy: sun4i-usb: Add support for the H616 USB PHY Andre Przywara
2021-05-19 10:41 ` [PATCH v6 14/17] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara
2021-05-24 12:02   ` Maxime Ripard
2021-06-07 12:59     ` Andre Przywara
2021-05-19 10:41 ` [PATCH v6 15/17] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding Andre Przywara
2021-05-19 10:41 ` [PATCH v6 16/17] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support Andre Przywara
2021-05-19 10:41 ` [PATCH v6 17/17] arm64: dts: allwinner: h616: Add X96 Mate TV box support Andre Przywara
2021-05-22  7:32   ` Jernej Škrabec

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210519104152.21119-11-andre.przywara@arm.com \
    --to=andre.przywara@arm.com \
    --cc=icenowy@aosc.io \
    --cc=jernej.skrabec@gmail.com \
    --cc=kishon@ti.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-phy@lists.infradead.org \
    --cc=linux-sunxi@googlegroups.com \
    --cc=linux-sunxi@lists.linux.dev \
    --cc=linux-usb@vger.kernel.org \
    --cc=megous@megous.com \
    --cc=mripard@kernel.org \
    --cc=robh@kernel.org \
    --cc=samuel@sholland.org \
    --cc=vkoul@kernel.org \
    --cc=wens@csie.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).