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Thu, 20 May 2021 15:37:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2579731B; Thu, 20 May 2021 08:37:42 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.7.235]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A2CAA3F73B; Thu, 20 May 2021 08:37:39 -0700 (PDT) Date: Thu, 20 May 2021 16:37:35 +0100 From: Mark Rutland To: Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, ardb@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, robin.murphy@arm.com Subject: Re: [PATCH v3 05/18] arm64: Do not enable uaccess for flush_icache_range Message-ID: <20210520153735.GM17233@C02TD0UTHF1T.local> References: <20210520124406.2731873-1-tabba@google.com> <20210520124406.2731873-6-tabba@google.com> <20210520140216.GG17233@C02TD0UTHF1T.local> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210520140216.GG17233@C02TD0UTHF1T.local> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210520_083744_730724_F198AE4F X-CRM114-Status: GOOD ( 31.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 20, 2021 at 03:02:16PM +0100, Mark Rutland wrote: > On Thu, May 20, 2021 at 01:43:53PM +0100, Fuad Tabba wrote: > > __flush_icache_range works on the kernel linear map, and doesn't > > need uaccess. The existing code is a side-effect of its current > > implementation with __flush_cache_user_range fallthrough. > > > > Instead of fallthrough to share the code, use a common macro for > > the two where the caller specifies an optional fixup label if > > user access is needed. If provided, this label would be used to > > generate an extable entry. > > > > No functional change intended. > > Possible performance impact due to the reduced number of > > instructions. > > > > Reported-by: Catalin Marinas > > Reported-by: Will Deacon > > Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/ > > Signed-off-by: Fuad Tabba > > I have one comment below, but either way this looks good to me, so: > > Acked-by: Mark Rutland > > > --- > > arch/arm64/mm/cache.S | 64 +++++++++++++++++++++++++++---------------- > > 1 file changed, 41 insertions(+), 23 deletions(-) > > > > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > > index 5ff8dfa86975..c6bc3b8138e1 100644 > > --- a/arch/arm64/mm/cache.S > > +++ b/arch/arm64/mm/cache.S > > @@ -14,6 +14,41 @@ > > #include > > #include > > > > +/* > > + * __flush_cache_range(start,end) [fixup] > > + * > > + * Ensure that the I and D caches are coherent within specified region. > > + * This is typically used when code has been written to a memory region, > > + * and will be executed. > > + * > > + * - start - virtual start address of region > > + * - end - virtual end address of region > > + * - fixup - optional label to branch to on user fault > > + */ > > +.macro __flush_cache_range, fixup > > +alternative_if ARM64_HAS_CACHE_IDC > > + dsb ishst > > + b .Ldc_skip_\@ > > +alternative_else_nop_endif > > + dcache_line_size x2, x3 > > + sub x3, x2, #1 > > + bic x4, x0, x3 > > +.Ldc_loop_\@: > > +user_alt "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE, \fixup > > + add x4, x4, x2 > > + cmp x4, x1 > > + b.lo .Ldc_loop_\@ > > + dsb ish > > As on the prior patch, I reckon it'd be nicer overall to align with the > *by_line macros and have an explicit _cond_extable here, e.g. > > | .Ldc_op\@: > | alternative_insn "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE > | add x4, x4, x2 > | cmp x4, x1 > | b.lo .Ldc_op\@ > | dsb ish > | ... > | // just before the .endm > | _cond_extable .Ldc_op\@, \fixup > > ... and with some rework it might be possible to use dcache_by_line_op > directly here (it currently clobbers the base and end, so can't be used > as-is). Having thought about this a bit more, it's simple enough to do that now: | alternative_if ARM64_HAS_CACHE_IDC | dsb ishst | b .Ldc_skip_\@ | alternative_else_nop_endif | mov x0, x2 | add x3, x0, x1 | dcache_by_line_op cvau, ishst, x2, x3, x4, x5, \fixup | .Ldc_skip_\@ ... and when we just need to change the ADD to a MOV when we change the macro to take the end in x1. Note that dcache_by_line_op will automatically upgrade 'cvau' to 'civac' when ARM64_WORKAROUND_CLEAN_CACHE is present, so the resulting logic is the same. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel