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Thu, 20 May 2021 15:48:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22C1931B; Thu, 20 May 2021 08:48:32 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.7.235]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 62FC93F73B; Thu, 20 May 2021 08:48:29 -0700 (PDT) Date: Thu, 20 May 2021 16:48:26 +0100 From: Mark Rutland To: Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, ardb@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, robin.murphy@arm.com Subject: Re: [PATCH v3 11/18] arm64: dcache_by_line_op to take end parameter instead of size Message-ID: <20210520154826.GO17233@C02TD0UTHF1T.local> References: <20210520124406.2731873-1-tabba@google.com> <20210520124406.2731873-12-tabba@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210520124406.2731873-12-tabba@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210520_084834_740846_A3D49DA0 X-CRM114-Status: GOOD ( 18.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 20, 2021 at 01:43:59PM +0100, Fuad Tabba wrote: > To be consistent with other functions with similar names and > functionality in cacheflush.h, cache.S, and cachetlb.rst, change > to specify the range in terms of start and end, as opposed to > start and size. > > No functional change intended. > > Reported-by: Will Deacon > Signed-off-by: Fuad Tabba Acked-by: Mark Rutland Mark. > --- > arch/arm64/include/asm/assembler.h | 27 +++++++++++++-------------- > arch/arm64/kvm/hyp/nvhe/cache.S | 1 + > arch/arm64/mm/cache.S | 5 +++++ > 3 files changed, 19 insertions(+), 14 deletions(-) > > diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h > index ced791124b28..c4cecf85dccf 100644 > --- a/arch/arm64/include/asm/assembler.h > +++ b/arch/arm64/include/asm/assembler.h > @@ -397,40 +397,39 @@ alternative_endif > > /* > * Macro to perform a data cache maintenance for the interval > - * [addr, addr + size) > + * [start, end) > * > * op: operation passed to dc instruction > * domain: domain used in dsb instruciton > - * addr: starting virtual address of the region > - * size: size of the region > + * start: starting virtual address of the region > + * end: end virtual address of the region > * fixup: optional label to branch to on user fault > - * Corrupts: addr, size, tmp1, tmp2 > + * Corrupts: start, end, tmp1, tmp2 > */ > - .macro dcache_by_line_op op, domain, addr, size, tmp1, tmp2, fixup > + .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup > dcache_line_size \tmp1, \tmp2 > - add \size, \addr, \size > sub \tmp2, \tmp1, #1 > - bic \addr, \addr, \tmp2 > + bic \start, \start, \tmp2 > .Ldcache_op\@: > .ifc \op, cvau > - __dcache_op_workaround_clean_cache \op, \addr > + __dcache_op_workaround_clean_cache \op, \start > .else > .ifc \op, cvac > - __dcache_op_workaround_clean_cache \op, \addr > + __dcache_op_workaround_clean_cache \op, \start > .else > .ifc \op, cvap > - sys 3, c7, c12, 1, \addr // dc cvap > + sys 3, c7, c12, 1, \start // dc cvap > .else > .ifc \op, cvadp > - sys 3, c7, c13, 1, \addr // dc cvadp > + sys 3, c7, c13, 1, \start // dc cvadp > .else > - dc \op, \addr > + dc \op, \start > .endif > .endif > .endif > .endif > - add \addr, \addr, \tmp1 > - cmp \addr, \size > + add \start, \start, \tmp1 > + cmp \start, \end > b.lo .Ldcache_op\@ > dsb \domain > > diff --git a/arch/arm64/kvm/hyp/nvhe/cache.S b/arch/arm64/kvm/hyp/nvhe/cache.S > index 36cef6915428..3bcfa3cac46f 100644 > --- a/arch/arm64/kvm/hyp/nvhe/cache.S > +++ b/arch/arm64/kvm/hyp/nvhe/cache.S > @@ -8,6 +8,7 @@ > #include > > SYM_FUNC_START_PI(__flush_dcache_area) > + add x1, x0, x1 > dcache_by_line_op civac, sy, x0, x1, x2, x3 > ret > SYM_FUNC_END_PI(__flush_dcache_area) > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > index 5170d9ab450a..3b5461a32b85 100644 > --- a/arch/arm64/mm/cache.S > +++ b/arch/arm64/mm/cache.S > @@ -115,6 +115,7 @@ SYM_FUNC_END(invalidate_icache_range) > * - size - size in question > */ > SYM_FUNC_START_PI(__flush_dcache_area) > + add x1, x0, x1 > dcache_by_line_op civac, sy, x0, x1, x2, x3 > ret > SYM_FUNC_END_PI(__flush_dcache_area) > @@ -133,6 +134,7 @@ alternative_if ARM64_HAS_CACHE_IDC > dsb ishst > ret > alternative_else_nop_endif > + add x1, x0, x1 > dcache_by_line_op cvau, ish, x0, x1, x2, x3 > ret > SYM_FUNC_END(__clean_dcache_area_pou) > @@ -194,6 +196,7 @@ SYM_FUNC_START_PI(__clean_dcache_area_poc) > * - start - virtual start address of region > * - size - size in question > */ > + add x1, x0, x1 > dcache_by_line_op cvac, sy, x0, x1, x2, x3 > ret > SYM_FUNC_END_PI(__clean_dcache_area_poc) > @@ -212,6 +215,7 @@ SYM_FUNC_START_PI(__clean_dcache_area_pop) > alternative_if_not ARM64_HAS_DCPOP > b __clean_dcache_area_poc > alternative_else_nop_endif > + add x1, x0, x1 > dcache_by_line_op cvap, sy, x0, x1, x2, x3 > ret > SYM_FUNC_END_PI(__clean_dcache_area_pop) > @@ -225,6 +229,7 @@ SYM_FUNC_END_PI(__clean_dcache_area_pop) > * - size - size in question > */ > SYM_FUNC_START_PI(__dma_flush_area) > + add x1, x0, x1 > dcache_by_line_op civac, sy, x0, x1, x2, x3 > ret > SYM_FUNC_END_PI(__dma_flush_area) > -- > 2.31.1.751.gd2f1c929bd-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel