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* [PATCH 0/2] arm64: imx8: fix booting with lastest nxp flash.bin
@ 2021-05-21  3:12 Dong Aisheng
  2021-05-21  3:12 ` [PATCH 1/2] clk: imx: scu: add enet rgmii gpr clocks Dong Aisheng
  2021-05-21  3:12 ` [PATCH 2/2] arm64: dts: imx8: conn: fix enet clock setting Dong Aisheng
  0 siblings, 2 replies; 6+ messages in thread
From: Dong Aisheng @ 2021-05-21  3:12 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: dongas86, linux-imx, shawnguo, kernel, festevam, devicetree,
	Dong Aisheng

There's enet clock incorrect setting issue in upstream kernel which
will cause kernel boot hanged on mouting NFS rootfs due to enet can't
work properly if using latest nxp flash.bin.
(Using old nxp flash.bin (e.g. 4.14 release), don't have this issue
cause bootloader did some tricks.)

This patchset aims to fix it.

The two patches has no build dependence and can be appied separately to clk
and arch tree.

However, this patchset can't apply for stable tree cause it still depends on
another patchset in clk tree.
https://patchwork.kernel.org/project/linux-clk/patch/20210423033334.3317992-4-aisheng.dong@nxp.com/

Dong Aisheng (2):
  clk: imx: scu: add enet rgmii gpr clocks
  arm64: dts: imx8: conn: fix enet clock setting

 .../boot/dts/freescale/imx8-ss-conn.dtsi      | 50 ++++++++++++-------
 drivers/clk/imx/clk-imx8qxp.c                 | 22 ++++++--
 2 files changed, 50 insertions(+), 22 deletions(-)

-- 
2.25.1


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^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 1/2] clk: imx: scu: add enet rgmii gpr clocks
  2021-05-21  3:12 [PATCH 0/2] arm64: imx8: fix booting with lastest nxp flash.bin Dong Aisheng
@ 2021-05-21  3:12 ` Dong Aisheng
  2021-05-26 10:34   ` Abel Vesa
  2021-05-21  3:12 ` [PATCH 2/2] arm64: dts: imx8: conn: fix enet clock setting Dong Aisheng
  1 sibling, 1 reply; 6+ messages in thread
From: Dong Aisheng @ 2021-05-21  3:12 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: dongas86, linux-imx, shawnguo, kernel, festevam, devicetree,
	Dong Aisheng, Abel Vesa, Stephen Boyd

enet tx clk actually is sourced from a gpr divider, not default enet
clk. Add enet grp clocks for user to use correctly.

Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 drivers/clk/imx/clk-imx8qxp.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 88cc737ee125..f3cdd6449212 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -25,6 +25,16 @@ static const char *dc0_sels[] = {
 	"dc0_bypass0_clk",
 };
 
+static const char *enet0_rgmii_txc_sels[] = {
+	"enet0_ref_div",
+	"dummy",
+};
+
+static const char *enet1_rgmii_txc_sels[] = {
+	"enet1_ref_div",
+	"dummy",
+};
+
 static int imx8qxp_clk_probe(struct platform_device *pdev)
 {
 	struct device_node *ccm_node = pdev->dev.of_node;
@@ -80,12 +90,16 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
 	imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
 	imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
-	imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
+	imx_clk_divider_gpr_scu("enet0_ref_div", "enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV);
+	imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);
 	imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
-	imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
-	imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
+	imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
+	imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);
+	imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);
 	imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
-	imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
+	imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
 	imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
 	imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
 	imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
-- 
2.25.1


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^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/2] arm64: dts: imx8: conn: fix enet clock setting
  2021-05-21  3:12 [PATCH 0/2] arm64: imx8: fix booting with lastest nxp flash.bin Dong Aisheng
  2021-05-21  3:12 ` [PATCH 1/2] clk: imx: scu: add enet rgmii gpr clocks Dong Aisheng
@ 2021-05-21  3:12 ` Dong Aisheng
  2021-05-23  5:34   ` Shawn Guo
  1 sibling, 1 reply; 6+ messages in thread
From: Dong Aisheng @ 2021-05-21  3:12 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: dongas86, linux-imx, shawnguo, kernel, festevam, devicetree,
	Dong Aisheng, Abel Vesa, Stephen Boyd

enet_clk_ref actually is sourced from internal gpr clocks
which needs a default rate. Also update enet lpcg clock
output names to be more straightforward.

Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 .../boot/dts/freescale/imx8-ss-conn.dtsi      | 50 ++++++++++++-------
 1 file changed, 32 insertions(+), 18 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index e1e81ca0ca69..a79f42a9618e 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -77,9 +77,12 @@ fec1: ethernet@5b040000 {
 			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
 			 <&enet0_lpcg IMX_LPCG_CLK_2>,
-			 <&enet0_lpcg IMX_LPCG_CLK_1>,
+			 <&enet0_lpcg IMX_LPCG_CLK_3>,
 			 <&enet0_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+		assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
+				  <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
+		assigned-clock-rates = <250000000>, <125000000>;
 		fsl,num-tx-queues=<3>;
 		fsl,num-rx-queues=<3>;
 		power-domains = <&pd IMX_SC_R_ENET_0>;
@@ -94,9 +97,12 @@ fec2: ethernet@5b050000 {
 				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
 			 <&enet1_lpcg IMX_LPCG_CLK_2>,
-			 <&enet1_lpcg IMX_LPCG_CLK_1>,
+			 <&enet1_lpcg IMX_LPCG_CLK_3>,
 			 <&enet1_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+				  <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
+		assigned-clock-rates = <250000000>, <125000000>;
 		fsl,num-tx-queues=<3>;
 		fsl,num-rx-queues=<3>;
 		power-domains = <&pd IMX_SC_R_ENET_1>;
@@ -152,15 +158,19 @@ enet0_lpcg: clock-controller@5b230000 {
 		#clock-cells = <1>;
 		clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
 			 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
-			 <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+			 <&conn_axi_clk>,
+			 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
+			 <&conn_ipg_clk>,
+			 <&conn_ipg_clk>;
 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
-				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
-				<IMX_LPCG_CLK_5>;
-		clock-output-names = "enet0_ipg_root_clk",
-				     "enet0_tx_clk",
-				     "enet0_ahb_clk",
-				     "enet0_ipg_clk",
-				     "enet0_ipg_s_clk";
+				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
+				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
+		clock-output-names = "enet0_lpcg_timer_clk",
+				     "enet0_lpcg_txc_sampling_clk",
+				     "enet0_lpcg_ahb_clk",
+				     "enet0_lpcg_rgmii_txc_clk",
+				     "enet0_lpcg_ipg_clk",
+				     "enet0_lpcg_ipg_s_clk";
 		power-domains = <&pd IMX_SC_R_ENET_0>;
 	};
 
@@ -170,15 +180,19 @@ enet1_lpcg: clock-controller@5b240000 {
 		#clock-cells = <1>;
 		clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
 			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
-			 <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+			 <&conn_axi_clk>,
+			 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
+			 <&conn_ipg_clk>,
+			 <&conn_ipg_clk>;
 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
-				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
-				<IMX_LPCG_CLK_5>;
-		clock-output-names = "enet1_ipg_root_clk",
-				     "enet1_tx_clk",
-				     "enet1_ahb_clk",
-				     "enet1_ipg_clk",
-				     "enet1_ipg_s_clk";
+				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
+				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
+		clock-output-names = "enet1_lpcg_timer_clk",
+				     "enet1_lpcg_txc_sampling_clk",
+				     "enet1_lpcg_ahb_clk",
+				     "enet1_lpcg_rgmii_txc_clk",
+				     "enet1_lpcg_ipg_clk",
+				     "enet1_lpcg_ipg_s_clk";
 		power-domains = <&pd IMX_SC_R_ENET_1>;
 	};
 };
-- 
2.25.1


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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/2] arm64: dts: imx8: conn: fix enet clock setting
  2021-05-21  3:12 ` [PATCH 2/2] arm64: dts: imx8: conn: fix enet clock setting Dong Aisheng
@ 2021-05-23  5:34   ` Shawn Guo
  0 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2021-05-23  5:34 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: linux-arm-kernel, dongas86, linux-imx, kernel, festevam,
	devicetree, Abel Vesa, Stephen Boyd

On Fri, May 21, 2021 at 11:12:48AM +0800, Dong Aisheng wrote:
> enet_clk_ref actually is sourced from internal gpr clocks
> which needs a default rate. Also update enet lpcg clock
> output names to be more straightforward.
> 
> Cc: Abel Vesa <abel.vesa@nxp.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Applied, thanks.

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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/2] clk: imx: scu: add enet rgmii gpr clocks
  2021-05-21  3:12 ` [PATCH 1/2] clk: imx: scu: add enet rgmii gpr clocks Dong Aisheng
@ 2021-05-26 10:34   ` Abel Vesa
  2021-05-26 10:46     ` Abel Vesa
  0 siblings, 1 reply; 6+ messages in thread
From: Abel Vesa @ 2021-05-26 10:34 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: linux-arm-kernel, dongas86, linux-imx, shawnguo, kernel,
	festevam, devicetree, Stephen Boyd

On 21-05-21 11:12:47, Dong Aisheng wrote:
> enet tx clk actually is sourced from a gpr divider, not default enet
> clk. Add enet grp clocks for user to use correctly.
> 
> Cc: Abel Vesa <abel.vesa@nxp.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

I'm OK with this:

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/clk-imx8qxp.c | 22 ++++++++++++++++++----
>  1 file changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> index 88cc737ee125..f3cdd6449212 100644
> --- a/drivers/clk/imx/clk-imx8qxp.c
> +++ b/drivers/clk/imx/clk-imx8qxp.c
> @@ -25,6 +25,16 @@ static const char *dc0_sels[] = {
>  	"dc0_bypass0_clk",
>  };
>  
> +static const char *enet0_rgmii_txc_sels[] = {
> +	"enet0_ref_div",
> +	"dummy",
> +};
> +
> +static const char *enet1_rgmii_txc_sels[] = {
> +	"enet1_ref_div",
> +	"dummy",
> +};
> +
>  static int imx8qxp_clk_probe(struct platform_device *pdev)
>  {
>  	struct device_node *ccm_node = pdev->dev.of_node;
> @@ -80,12 +90,16 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
>  	imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
>  	imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
>  	imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
> -	imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_divider_gpr_scu("enet0_ref_div", "enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV);
> +	imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);
>  	imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
> -	imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
> -	imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
> +	imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);
> +	imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);
>  	imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
> -	imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
> +	imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
>  	imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
>  	imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
>  	imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
> -- 
> 2.25.1
> 

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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/2] clk: imx: scu: add enet rgmii gpr clocks
  2021-05-26 10:34   ` Abel Vesa
@ 2021-05-26 10:46     ` Abel Vesa
  0 siblings, 0 replies; 6+ messages in thread
From: Abel Vesa @ 2021-05-26 10:46 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: linux-arm-kernel, dongas86, linux-imx, shawnguo, kernel,
	festevam, devicetree, Stephen Boyd

On 21-05-26 13:34:19, Abel Vesa wrote:
> On 21-05-21 11:12:47, Dong Aisheng wrote:
> > enet tx clk actually is sourced from a gpr divider, not default enet
> > clk. Add enet grp clocks for user to use correctly.
> > 
> > Cc: Abel Vesa <abel.vesa@nxp.com>
> > Cc: Stephen Boyd <sboyd@kernel.org>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> 
> I'm OK with this:
> 
> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> 

Applied this one, thanks.

> > ---
> >  drivers/clk/imx/clk-imx8qxp.c | 22 ++++++++++++++++++----
> >  1 file changed, 18 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> > index 88cc737ee125..f3cdd6449212 100644
> > --- a/drivers/clk/imx/clk-imx8qxp.c
> > +++ b/drivers/clk/imx/clk-imx8qxp.c
> > @@ -25,6 +25,16 @@ static const char *dc0_sels[] = {
> >  	"dc0_bypass0_clk",
> >  };
> >  
> > +static const char *enet0_rgmii_txc_sels[] = {
> > +	"enet0_ref_div",
> > +	"dummy",
> > +};
> > +
> > +static const char *enet1_rgmii_txc_sels[] = {
> > +	"enet1_ref_div",
> > +	"dummy",
> > +};
> > +
> >  static int imx8qxp_clk_probe(struct platform_device *pdev)
> >  {
> >  	struct device_node *ccm_node = pdev->dev.of_node;
> > @@ -80,12 +90,16 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
> >  	imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
> >  	imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
> >  	imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
> > -	imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
> > +	imx_clk_scu("enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
> > +	imx_clk_divider_gpr_scu("enet0_ref_div", "enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV);
> > +	imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);
> >  	imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
> > -	imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
> > -	imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
> > +	imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
> > +	imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
> > +	imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);
> > +	imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);
> >  	imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
> > -	imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
> > +	imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
> >  	imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
> >  	imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
> >  	imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
> > -- 
> > 2.25.1
> > 

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^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-05-26 13:13 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-21  3:12 [PATCH 0/2] arm64: imx8: fix booting with lastest nxp flash.bin Dong Aisheng
2021-05-21  3:12 ` [PATCH 1/2] clk: imx: scu: add enet rgmii gpr clocks Dong Aisheng
2021-05-26 10:34   ` Abel Vesa
2021-05-26 10:46     ` Abel Vesa
2021-05-21  3:12 ` [PATCH 2/2] arm64: dts: imx8: conn: fix enet clock setting Dong Aisheng
2021-05-23  5:34   ` Shawn Guo

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