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From: Zhen Lei <thunder.leizhen@huawei.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-mediatek <linux-mediatek@lists.infradead.org>,
	devicetree <devicetree@vger.kernel.org>
Cc: Zhen Lei <thunder.leizhen@huawei.com>
Subject: [PATCH 1/1] arm64: dts: mt8173-elm: Correct the value of the property 'reg'
Date: Fri, 21 May 2021 17:52:43 +0800	[thread overview]
Message-ID: <20210521095243.8527-1-thunder.leizhen@huawei.com> (raw)

The values of property '#address-cells' and '#size-cells' defined in the
parent node are both 1. Therefore, the value 0 of the upper 32 bits cannot
be written.

This error is detected by reg.yaml, the information reported is as
follows:

arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml:
 mt6397: syscfg_pctl_pmic@c000:reg:0: [0, 49152, 0, 264] is too long

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
index 21452c51a20a813..9bc02ea020f10e8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
@@ -1112,7 +1112,7 @@ rtc: mt6397rtc {
 		syscfg_pctl_pmic: syscfg_pctl_pmic@c000 {
 			compatible = "mediatek,mt6397-pctl-pmic-syscfg",
 				     "syscon";
-			reg = <0 0x0000c000 0 0x0108>;
+			reg = <0x0000c000 0x0108>;
 		};
 	};
 };
-- 
2.26.0.106.g9fadedd



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                 reply	other threads:[~2021-05-21  9:56 UTC|newest]

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