From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FEB9C433B4 for ; Fri, 21 May 2021 10:51:20 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E0301613B6 for ; Fri, 21 May 2021 10:51:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E0301613B6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lxs15fx2Q4nAD4tvjX+5vGbvG1jznOejiLdFPpGr284=; b=a9uwW6zyLAgc/9DRbiCBzALiR6 4UmyORU4TQx2tJKxHxDffR+GBTi2vOL+bQJx1ticARAaDOcoCYiPQZdD4fnN6DeoUV7Sby3dVhgu8 dnCWUgSphK7iOMLzi/3wUXOY1XwxUI//l6OBy2AMAt55MRnSrLkNPyOZxbGdxyIw1h98VoKftvw1l b4wKARd5FEt/vpoljeuX4NEHxRMgd9EkufYOpr29wmKXvBYpwPlrVIcZ4Eh8+e6QSNbhi35SQIIM6 bRDwmLRzXgJwLmzD8AUN8fdoHcPrRF88B0qAUlV9APUfwBm+XTH9sFAsfDbLB2SyG/CKlWuOjRyyG 8DlggWgg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lk2i7-0050Cx-Ge; Fri, 21 May 2021 10:48:55 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lk2hi-00505I-V1 for linux-arm-kernel@desiato.infradead.org; Fri, 21 May 2021 10:48:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=KiXUhnQj0xz9y9hznwubzQmx28u8Uk55GtMTk/LYj5c=; b=erY4Z5q2UJ/y+cx3H7GGlMiIcq 9JwSQnVjqWH5ljJPOGfAyj50FAvQQEuyEWi5ZkzJScL94e0E4tEmWWK/xQaNgpkKYqDiKFxVYGRKH JT1LP8R9NGfWmY2Jikcmi65E2L8js8CSrfamA8dayeyZ0YS/Kjtb9ciaMCySV1v8Vv2/CscOURubb Di1SJMg0PHSen6vxO66vOMX3Zet1aDZmSwSMxv+N/JniaRJe2lDWg+B36LtHAv2kPPCwDTekuf45q lk7s0sdd5LhKIW9sm5c3ZQxHyeA5BYeatEiyz++KZ5BP2DIEjpwWt0AlFo6CyEfVBfP/rmLNhosQW BXsz4BDw==; Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lk2he-00H37v-QQ for linux-arm-kernel@lists.infradead.org; Fri, 21 May 2021 10:48:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CE59E150C; Fri, 21 May 2021 03:48:25 -0700 (PDT) Received: from optiplex-7070.shanghai.arm.com (optiplex-7070.shanghai.arm.com [10.169.188.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 049793F73D; Fri, 21 May 2021 03:48:23 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com, andre.przywara@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH v2 2/8] aarch64: Rename labels and prepare for lower EL booting Date: Fri, 21 May 2021 18:48:01 +0800 Message-Id: <20210521104807.138269-3-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210521104807.138269-1-jaxson.han@arm.com> References: <20210521104807.138269-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210521_034826_996747_DBA0AF43 X-CRM114-Status: GOOD ( 12.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Prepare for booting from lower EL. Rename *_el3 relavant labels with *_el_max and *_no_el3 with *_keep_el. Since the original _no_el3 means "We neither do init sequence at this highest EL nor drop to lower EL when entering to kernel", we rename it with _keep_el to make it more clear for lower EL initialisation. Signed-off-by: Jaxson Han --- arch/aarch64/boot.S | 33 ++++++++++++++++++++++----------- arch/aarch64/include/asm/cpu.h | 3 +++ arch/aarch64/psci.S | 13 +++++++------ arch/aarch64/spin.S | 8 ++++---- 4 files changed, 36 insertions(+), 21 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index a9264de..e4f5f3d 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -12,7 +12,7 @@ .section .init .globl _start - .globl jump_kernel + .globl jump_kernel _start: cpuid x0, x1 @@ -22,20 +22,31 @@ _start: bl setup_stack /* - * EL3 initialisation + * Boot sequence + * If CurrentEL == EL3, then goto EL3 initialisation and drop to + * lower EL before entering the kernel. + * Else, no initialisation and keep the current EL before + * entering the kernel. */ mrs x0, CurrentEL cmp x0, #CURRENTEL_EL3 - b.eq 1f + beq el3_init + /* + * We stay in the current EL for entering the kernel + */ mov w0, #1 - ldr x1, =flag_no_el3 + ldr x1, =flag_keep_el str w0, [x1] bl setup_stack - b start_no_el3 + b start_keep_el -1: mov x0, #0x30 // RES1 + /* + * EL3 initialisation + */ +el3_init: + mov x0, #0x30 // RES1 orr x0, x0, #(1 << 0) // Non-secure EL1 orr x0, x0, #(1 << 8) // HVC enable @@ -114,7 +125,7 @@ _start: bl gic_secure_init - b start_el3 + b start_el_max err_invalid_id: b . @@ -141,7 +152,7 @@ jump_kernel: bl find_logical_id bl setup_stack // Reset stack pointer - ldr w0, flag_no_el3 + ldr w0, flag_keep_el cmp w0, #0 // Prepare Z flag mov x0, x20 @@ -150,9 +161,9 @@ jump_kernel: mov x3, x23 b.eq 1f - br x19 // No EL3 + br x19 // Keep current EL -1: mov x4, #SPSR_KERNEL +1: ldr w4, #SPSR_KERNEL /* * If bit 0 of the kernel address is set, we're entering in AArch32 @@ -168,5 +179,5 @@ jump_kernel: .data .align 3 -flag_no_el3: +flag_keep_el: .long 0 diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index ccb5397..2b3a0a4 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -11,6 +11,7 @@ #define MPIDR_ID_BITS 0xff00ffffff +#define CURRENTEL_EL2 (2 << 2) #define CURRENTEL_EL3 (3 << 2) /* @@ -24,6 +25,7 @@ #define SPSR_I (1 << 7) /* IRQ masked */ #define SPSR_F (1 << 6) /* FIQ masked */ #define SPSR_T (1 << 5) /* Thumb */ +#define SPSR_EL1H (5 << 0) /* EL1 Handler mode */ #define SPSR_EL2H (9 << 0) /* EL2 Handler mode */ #define SPSR_HYP (0x1a << 0) /* M[3:0] = hyp, M[4] = AArch32 */ @@ -42,6 +44,7 @@ #else #define SCTLR_EL1_RESET SCTLR_EL1_RES1 #define SPSR_KERNEL (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H) +#define SPSR_KERNEL_EL1 (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H) #endif #ifndef __ASSEMBLY__ diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S index 01ebe7d..ae02fd6 100644 --- a/arch/aarch64/psci.S +++ b/arch/aarch64/psci.S @@ -45,8 +45,8 @@ vector: .text - .globl start_no_el3 - .globl start_el3 + .globl start_keep_el + .globl start_el_max err_exception: b err_exception @@ -101,7 +101,7 @@ smc_exit: eret -start_el3: +start_el_max: ldr x0, =vector bl setup_vector @@ -111,10 +111,11 @@ start_el3: b psci_first_spin /* - * This PSCI implementation requires EL3. Without EL3 we'll only boot the - * primary cpu, all others will be trapped in an infinite loop. + * This PSCI implementation requires the highest EL(EL3 or Armv8-R EL2). + * Without the highest EL, we'll only boot the primary cpu, all others + * will be trapped in an infinite loop. */ -start_no_el3: +start_keep_el: cpuid x0, x1 bl find_logical_id cbz x0, psci_first_spin diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S index 72603cf..533177c 100644 --- a/arch/aarch64/spin.S +++ b/arch/aarch64/spin.S @@ -11,11 +11,11 @@ .text - .globl start_no_el3 - .globl start_el3 + .globl start_keep_el + .globl start_el_max -start_el3: -start_no_el3: +start_el_max: +start_keep_el: cpuid x0, x1 bl find_logical_id -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel