From: Mark Rutland <mark.rutland@arm.com>
To: Fuad Tabba <tabba@google.com>
Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org,
catalin.marinas@arm.com, maz@kernel.org, ardb@kernel.org,
james.morse@arm.com, alexandru.elisei@arm.com,
suzuki.poulose@arm.com, robin.murphy@arm.com
Subject: Re: [PATCH v4 04/18] arm64: Do not enable uaccess for flush_icache_range
Date: Mon, 24 May 2021 10:57:30 +0100 [thread overview]
Message-ID: <20210524095730.GB1040@C02TD0UTHF1T.local> (raw)
In-Reply-To: <20210524083001.2586635-5-tabba@google.com>
On Mon, May 24, 2021 at 09:29:47AM +0100, Fuad Tabba wrote:
> __flush_icache_range works on kernel addresses, and doesn't need
> uaccess. The existing code is a side-effect of its current
> implementation with __flush_cache_user_range fallthrough.
>
> Instead of fallthrough to share the code, use a common macro for
> the two where the caller specifies an optional fixup label if
> user access is needed. If provided, this label would be used to
> generate an extable entry.
>
> Simplify the code to use dcache_by_line_op, instead of
> replicating much of its functionality.
>
> No functional change intended.
> Possible performance impact due to the reduced number of
> instructions.
>
> Reported-by: Catalin Marinas <catalin.marinas@arm.com>
> Reported-by: Will Deacon <will@kernel.org>
> Reported-by: Mark Rutland <mark.rutland@arm.com>
> Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/
> Link: https://lore.kernel.org/linux-arm-kernel/20210521121846.GB1040@C02TD0UTHF1T.local/
> Signed-off-by: Fuad Tabba <tabba@google.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> ---
> arch/arm64/mm/cache.S | 57 ++++++++++++++++++++++++++-----------------
> 1 file changed, 34 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
> index 2d881f34dd9d..7c54bcbf5a36 100644
> --- a/arch/arm64/mm/cache.S
> +++ b/arch/arm64/mm/cache.S
> @@ -14,6 +14,34 @@
> #include <asm/alternative.h>
> #include <asm/asm-uaccess.h>
>
> +/*
> + * __flush_cache_range(start,end) [fixup]
> + *
> + * Ensure that the I and D caches are coherent within specified region.
> + * This is typically used when code has been written to a memory region,
> + * and will be executed.
> + *
> + * - start - virtual start address of region
> + * - end - virtual end address of region
> + * - fixup - optional label to branch to on user fault
> + */
> +.macro __flush_cache_range, fixup
> +alternative_if ARM64_HAS_CACHE_IDC
> + dsb ishst
> + b .Ldc_skip_\@
> +alternative_else_nop_endif
> + mov x2, x0
> + sub x3, x1, x0
> + dcache_by_line_op cvau, ish, x2, x3, x4, x5, \fixup
> +.Ldc_skip_\@:
> +alternative_if ARM64_HAS_CACHE_DIC
> + isb
> + b .Lic_skip_\@
> +alternative_else_nop_endif
> + invalidate_icache_by_line x0, x1, x2, x3, \fixup
> +.Lic_skip_\@:
> +.endm
> +
> /*
> * flush_icache_range(start,end)
> *
> @@ -25,7 +53,9 @@
> * - end - virtual end address of region
> */
> SYM_FUNC_START(__flush_icache_range)
> - /* FALLTHROUGH */
> + __flush_cache_range
> + ret
> +SYM_FUNC_END(__flush_icache_range)
>
> /*
> * __flush_cache_user_range(start,end)
> @@ -39,34 +69,15 @@ SYM_FUNC_START(__flush_icache_range)
> */
> SYM_FUNC_START(__flush_cache_user_range)
> uaccess_ttbr0_enable x2, x3, x4
> -alternative_if ARM64_HAS_CACHE_IDC
> - dsb ishst
> - b 7f
> -alternative_else_nop_endif
> - dcache_line_size x2, x3
> - sub x3, x2, #1
> - bic x4, x0, x3
> -1:
> -user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE
> - add x4, x4, x2
> - cmp x4, x1
> - b.lo 1b
> - dsb ish
>
> -7:
> -alternative_if ARM64_HAS_CACHE_DIC
> - isb
> - b 8f
> -alternative_else_nop_endif
> - invalidate_icache_by_line x0, x1, x2, x3, 9f
> -8: mov x0, #0
> + __flush_cache_range 2f
> + mov x0, xzr
> 1:
> uaccess_ttbr0_disable x1, x2
> ret
> -9:
> +2:
> mov x0, #-EFAULT
> b 1b
> -SYM_FUNC_END(__flush_icache_range)
> SYM_FUNC_END(__flush_cache_user_range)
>
> /*
> --
> 2.31.1.818.g46aad6cb9e-goog
>
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next prev parent reply other threads:[~2021-05-24 16:50 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-24 8:29 [PATCH v4 00/18] Tidy up cache.S Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 01/18] arm64: assembler: replace `kaddr` with `addr` Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 02/18] arm64: assembler: add conditional cache fixups Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 03/18] arm64: Apply errata to swsusp_arch_suspend_exit Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 04/18] arm64: Do not enable uaccess for flush_icache_range Fuad Tabba
2021-05-24 9:02 ` Ard Biesheuvel
2021-05-24 9:20 ` Fuad Tabba
2021-05-24 9:41 ` Ard Biesheuvel
2021-05-24 9:53 ` Mark Rutland
2021-05-24 9:57 ` Mark Rutland [this message]
2021-05-25 11:20 ` Catalin Marinas
2021-05-24 8:29 ` [PATCH v4 05/18] arm64: Do not enable uaccess for invalidate_icache_range Fuad Tabba
2021-05-25 11:21 ` Catalin Marinas
2021-05-24 8:29 ` [PATCH v4 06/18] arm64: Downgrade flush_icache_range to invalidate Fuad Tabba
2021-05-25 11:21 ` Catalin Marinas
2021-05-24 8:29 ` [PATCH v4 07/18] arm64: assembler: remove user_alt Fuad Tabba
2021-05-24 9:58 ` Mark Rutland
2021-05-24 8:29 ` [PATCH v4 08/18] arm64: Move documentation of dcache_by_line_op Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 09/18] arm64: Fix comments to refer to correct function __flush_icache_range Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 10/18] arm64: __inval_dcache_area to take end parameter instead of size Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 11/18] arm64: dcache_by_line_op " Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 12/18] arm64: __flush_dcache_area " Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 13/18] arm64: __clean_dcache_area_poc " Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 14/18] arm64: __clean_dcache_area_pop " Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 15/18] arm64: __clean_dcache_area_pou " Fuad Tabba
2021-05-24 8:29 ` [PATCH v4 16/18] arm64: sync_icache_aliases " Fuad Tabba
2021-05-24 8:30 ` [PATCH v4 17/18] arm64: Fix cache maintenance function comments Fuad Tabba
2021-05-24 8:30 ` [PATCH v4 18/18] arm64: Rename arm64-internal cache maintenance functions Fuad Tabba
2021-05-24 9:47 ` [PATCH v4 00/18] Tidy up cache.S Ard Biesheuvel
2021-05-25 18:58 ` Will Deacon
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