From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A640C2B9F8 for ; Tue, 25 May 2021 17:41:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D96C6113B for ; Tue, 25 May 2021 17:41:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4D96C6113B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TK9VCQqQaSzcAf606vggdvTO4J9gLNzMGXnobC1gGl4=; b=bk7QacnQqmJyCF IWsRXkKSvtfIAHkmX8g0Q70B/4KdEUUKB9VDEvsUxLFREywdwn0KdcYi0UHtEHc+3stpvzmLkiW10 eMlepiCpvJBldG3B8T4K6+SW10A8914AHiGcnxNpE9us4BfgoNdl0zWS0AFV26k3Kh5uu1KvQN+kI ciVbJUtcj8cKEu2ChjrrjTarXp2pVtN6Z/kUzNe2KEWAuaPn8FlHXeriAkjjl5kxlGhGHGXOQJEaY wYiBeWggdQ9niK3qUTqGp6/sQZ4GBxKN4zea3vn1xrctYQwDmjxHplEaCGT7SftMXPFlLK8OS3EvT /0ZjxrFrh/s/UFMlgEuA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1llb0i-006wn2-5C; Tue, 25 May 2021 17:38:33 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1llavi-006ugf-QJ for linux-arm-kernel@lists.infradead.org; Tue, 25 May 2021 17:33:24 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C2E9B1516; Tue, 25 May 2021 10:33:16 -0700 (PDT) Received: from e113632-lin.cambridge.arm.com (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B1F8A3F73B; Tue, 25 May 2021 10:33:15 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [RFC PATCH v2 01/10] genirq: Add chip flag to denote automatic IRQ (un)masking Date: Tue, 25 May 2021 18:32:46 +0100 Message-Id: <20210525173255.620606-2-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525173255.620606-1-valentin.schneider@arm.com> References: <20210525173255.620606-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210525_103323_004251_8357C048 X-CRM114-Status: GOOD ( 12.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some IRQ chips such as the Arm GICs automagically mask / unmask an IRQ during the handling of said IRQ. This renders further mask / unmask operations within the flow handlers redundant, which we do want to leverage as masking by itself is not cheap (Distributor access via MMIO for GICs). This is different from having a chip->irq_mask_ack() callback as this masking is: - inherent to the chip->irq_ack() and *cannot* be omitted - a *different* masking state than chip->irq_mask() (chip->irq_mask() is idempotent, chip->irq_ack() really isn't) Add a chip flag, IRQCHIP_AUTOMASKS_FLOW, to denote chips with such behaviour. Add a new IRQ data flag, IRQD_IRQ_FLOW_MASKED, to keep this flow-induced mask state separate from regular mask / unmask operations (IRQD_IRQ_MASKED). Signed-off-by: Valentin Schneider --- include/linux/irq.h | 10 ++++++++++ kernel/irq/chip.c | 5 +++++ kernel/irq/debugfs.c | 2 ++ kernel/irq/internals.h | 5 +++++ 4 files changed, 22 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index 8e9a9ae471a6..ef179245a642 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -221,6 +221,8 @@ struct irq_data { * irq_chip::irq_set_affinity() when deactivated. * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set. + * IRQD_IRQ_FLOW_MASKED - Interrupt is masked by ACK. Only EOI can + * clear this. */ enum { IRQD_TRIGGER_MASK = 0xf, @@ -247,6 +249,7 @@ enum { IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28), IRQD_AFFINITY_ON_ACTIVATE = (1 << 29), IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30), + IRQD_IRQ_FLOW_MASKED = (1 << 31), }; #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) @@ -351,6 +354,11 @@ static inline bool irqd_irq_masked(struct irq_data *d) return __irqd_to_state(d) & IRQD_IRQ_MASKED; } +static inline bool irqd_irq_flow_masked(struct irq_data *d) +{ + return __irqd_to_state(d) & IRQD_IRQ_FLOW_MASKED; +} + static inline bool irqd_irq_inprogress(struct irq_data *d) { return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; @@ -569,6 +577,7 @@ struct irq_chip { * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs * in the suspend path if they are in disabled state + * IRQCHIP_AUTOMASKS_FLOW: chip->ack() masks and chip->eoi() unmasks */ enum { IRQCHIP_SET_TYPE_MASKED = (1 << 0), @@ -581,6 +590,7 @@ enum { IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), IRQCHIP_SUPPORTS_NMI = (1 << 8), IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), + IRQCHIP_AUTOMASKS_FLOW = (1 << 10), }; #include diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 7f04c7d8296e..21a21baa1366 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -173,6 +173,11 @@ static void irq_state_clr_masked(struct irq_desc *desc) irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); } +static void irq_state_clr_flow_masked(struct irq_desc *desc) +{ + irqd_clear(&desc->irq_data, IRQD_IRQ_FLOW_MASKED); +} + static void irq_state_clr_started(struct irq_desc *desc) { irqd_clear(&desc->irq_data, IRQD_IRQ_STARTED); diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c index e4cff358b437..3ae83622d701 100644 --- a/kernel/irq/debugfs.c +++ b/kernel/irq/debugfs.c @@ -58,6 +58,7 @@ static const struct irq_bit_descr irqchip_flags[] = { BIT_MASK_DESCR(IRQCHIP_SUPPORTS_LEVEL_MSI), BIT_MASK_DESCR(IRQCHIP_SUPPORTS_NMI), BIT_MASK_DESCR(IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND), + BIT_MASK_DESCR(IRQCHIP_AUTOMASKS_FLOW), }; static void @@ -103,6 +104,7 @@ static const struct irq_bit_descr irqdata_states[] = { BIT_MASK_DESCR(IRQD_IRQ_STARTED), BIT_MASK_DESCR(IRQD_IRQ_DISABLED), BIT_MASK_DESCR(IRQD_IRQ_MASKED), + BIT_MASK_DESCR(IRQD_IRQ_FLOW_MASKED), BIT_MASK_DESCR(IRQD_IRQ_INPROGRESS), BIT_MASK_DESCR(IRQD_PER_CPU), diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 54363527feea..b6c1cceddec0 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -245,6 +245,11 @@ static inline void irq_state_set_masked(struct irq_desc *desc) irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); } +static inline void irq_state_set_flow_masked(struct irq_desc *desc) +{ + irqd_set(&desc->irq_data, IRQD_IRQ_FLOW_MASKED); +} + #undef __irqd_to_state static inline void __kstat_incr_irqs_this_cpu(struct irq_desc *desc) -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel