From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0464CC2B9F8 for ; Tue, 25 May 2021 18:40:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BFB2361409 for ; Tue, 25 May 2021 18:40:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BFB2361409 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=InHyeu4AIJlTdfVD1s1WL2HP1brfGShy5XzRjUe9oZs=; b=3AAKY8qktaTJA2 0iz5thoz0U00z8JxajKLBQGULjw243wcCkow+R4kCh86qipCZ4WEKQPa6O9p7RzlzaK30GSttGOoJ ffUWDX2Ipqt7p13WhNmufC0QeczzbZ89VzDwS8pdlvKUIJrtkIlmRGIeqxrqR0x4Q62SVh/eeIhDl 8WuV4CkaQHZv6iHEeMA0qplP8540+AQ81Ny+kQ0O+SzoP1FNELvRuvT6nZnicVPrEk86ihLgALsmr p5KExkC3hRRNHfdBthj8uGiUMIumyy/owa2xR1+urX1KcwRfMu7VLXIpZ28MzhftKdPdPWzOLukuS nT2ZOCteaCUNhGxY/B/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1llbx4-007Kir-KU; Tue, 25 May 2021 18:38:50 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1llbsY-007IKq-66 for linux-arm-kernel@lists.infradead.org; Tue, 25 May 2021 18:34:12 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C0123169C; Tue, 25 May 2021 11:34:02 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B9BD23F719; Tue, 25 May 2021 11:34:01 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, james.morse@arm.com, joey.gouly@arm.com, mark.rutland@arm.com, maz@kernel.org, will@kernel.org Subject: [PATCH v3 09/20] arm64: entry: organise entry vectors consistently Date: Tue, 25 May 2021 19:32:51 +0100 Message-Id: <20210525183302.56293-10-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210525183302.56293-1-mark.rutland@arm.com> References: <20210525183302.56293-1-mark.rutland@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210525_113410_376206_529AA05A X-CRM114-Status: UNSURE ( 9.93 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In subsequent patches we'll rename the entry handlers based on their original EL, register width, and exception class. To do so, we need to make all 3 mandatory arguments to the `kernel_ventry` macro, and distinguish EL1h from EL1t. In preparation for this, let's make the current set of arguments mandatory, and move the `regsize` column before the branch label suffix, making the vectors easier to read column-wise. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Reviewed-by: Joey Gouly Cc: Catalin Marinas Cc: James Morse Cc: Marc Zyngier Cc: Will Deacon --- arch/arm64/kernel/entry.S | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index d5005af8da52..dd5319ade2db 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -54,7 +54,7 @@ #define BAD_FIQ 2 #define BAD_ERROR 3 - .macro kernel_ventry, el, label, regsize = 64 + .macro kernel_ventry, el:req, regsize:req, label:req .align 7 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 .if \el == 0 @@ -504,31 +504,31 @@ tsk .req x28 // current thread_info .align 11 SYM_CODE_START(vectors) - kernel_ventry 1, sync_invalid // Synchronous EL1t - kernel_ventry 1, irq_invalid // IRQ EL1t - kernel_ventry 1, fiq_invalid // FIQ EL1t - kernel_ventry 1, error_invalid // Error EL1t + kernel_ventry 1, 64, sync_invalid // Synchronous EL1t + kernel_ventry 1, 64, irq_invalid // IRQ EL1t + kernel_ventry 1, 64, fiq_invalid // FIQ EL1t + kernel_ventry 1, 64, error_invalid // Error EL1t - kernel_ventry 1, sync // Synchronous EL1h - kernel_ventry 1, irq // IRQ EL1h - kernel_ventry 1, fiq // FIQ EL1h - kernel_ventry 1, error // Error EL1h + kernel_ventry 1, 64, sync // Synchronous EL1h + kernel_ventry 1, 64, irq // IRQ EL1h + kernel_ventry 1, 64, fiq // FIQ EL1h + kernel_ventry 1, 64, error // Error EL1h - kernel_ventry 0, sync // Synchronous 64-bit EL0 - kernel_ventry 0, irq // IRQ 64-bit EL0 - kernel_ventry 0, fiq // FIQ 64-bit EL0 - kernel_ventry 0, error // Error 64-bit EL0 + kernel_ventry 0, 64, sync // Synchronous 64-bit EL0 + kernel_ventry 0, 64, irq // IRQ 64-bit EL0 + kernel_ventry 0, 64, fiq // FIQ 64-bit EL0 + kernel_ventry 0, 64, error // Error 64-bit EL0 #ifdef CONFIG_COMPAT - kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 - kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 - kernel_ventry 0, fiq_compat, 32 // FIQ 32-bit EL0 - kernel_ventry 0, error_compat, 32 // Error 32-bit EL0 + kernel_ventry 0, 32, sync_compat // Synchronous 32-bit EL0 + kernel_ventry 0, 32, irq_compat // IRQ 32-bit EL0 + kernel_ventry 0, 32, fiq_compat // FIQ 32-bit EL0 + kernel_ventry 0, 32, error_compat // Error 32-bit EL0 #else - kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 - kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 - kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 - kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 + kernel_ventry 0, 32, sync_invalid // Synchronous 32-bit EL0 + kernel_ventry 0, 32, irq_invalid // IRQ 32-bit EL0 + kernel_ventry 0, 32, fiq_invalid // FIQ 32-bit EL0 + kernel_ventry 0, 32, error_invalid // Error 32-bit EL0 #endif SYM_CODE_END(vectors) -- 2.11.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel