[PATCH v2 0/4] ASPEED sgpio driver enhancement.

[PATCH v2 0/4] ASPEED sgpio driver enhancement.

[Steven Lee]

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.

For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed dtsi to support the enhanced sgpio.
- Get the max number of sgpio that SoC supported from dts.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins.

Changes from v1:
* Fix yaml format issues.
* Fix issues reported by kernel test robot.

Please help to review.

Thanks,
Steven

Steven Lee (4):
  dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
  ARM: dts: aspeed-g6: Add SGPIO node.
  ARM: dts: aspeed-g5: Modify sgpio node for the enhanced sgpio driver.
  gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

 .../bindings/gpio/aspeed,sgpio.yaml           |  91 +++++++++
 .../devicetree/bindings/gpio/sgpio-aspeed.txt |  46 -----
 arch/arm/boot/dts/aspeed-g5.dtsi              |   3 +-
 arch/arm/boot/dts/aspeed-g6.dtsi              |  32 +++
 drivers/gpio/gpio-aspeed-sgpio.c              | 193 ++++++++++++------
 5 files changed, 250 insertions(+), 115 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
 delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt

-- 
2.17.1


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[PATCH v2 1/4] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.

[Steven Lee]

SGPIO bindings should be converted as yaml format.
In addition to the file conversion, a new property max-ngpios is
added in the yaml file as well.
The new property is required by the enhanced sgpio driver for
making the configuration of the max number of gpio pins more flexible.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 .../bindings/gpio/aspeed,sgpio.yaml           | 91 +++++++++++++++++++
 .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ----------
 2 files changed, 91 insertions(+), 46 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
 delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt

diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
new file mode 100644
index 000000000000..02eb0c5023e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed SGPIO controller
+
+maintainers:
+  - Andrew Jeffery <andrew@aj.id.au>
+
+description:
+  This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
+  AST2600 have two sgpio master one with 128 pins another one with 80 pins,
+  AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
+  GPIO pins can be programmed to support the following options
+  - Support interrupt option for each input port and various interrupt
+    sensitivity option (level-high, level-low, edge-high, edge-low)
+  - Support reset tolerance option for each output port
+  - Directly connected to APB bus and its shift clock is from APB bus clock
+    divided by a programmable value.
+  - Co-work with external signal-chained TTL components (74LV165/74LV595)
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2400-sgpiom
+      - aspeed,ast2500-sgpiom
+      - aspeed,ast2600-sgpiom
+
+  reg:
+    maxItems: 1
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  clocks:
+    maxItems: 1
+
+  ngpios:
+    minimum: 0
+    maximum: 128
+
+  max-ngpios:
+    description:
+      represents the number of actual hardware-supported GPIOs (ie,
+      slots within the clocked serial GPIO data). Since each HW GPIO is both an
+      input and an output, we provide max_ngpios * 2 lines on our gpiochip
+      device. We also use it to define the split between the inputs and
+      outputs; the inputs start at line 0, the outputs start at max_ngpios.
+    minimum: 0
+    maximum: 128
+
+  bus-frequency: true
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - '#gpio-cells'
+  - interrupts
+  - interrupt-controller
+  - ngpios
+  - max-ngpios
+  - clocks
+  - bus-frequency
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/aspeed-clock.h>
+    sgpio: sgpio@1e780200 {
+        #gpio-cells = <2>;
+        compatible = "aspeed,ast2500-sgpiom";
+        gpio-controller;
+        interrupts = <40>;
+        reg = <0x1e780200 0x0100>;
+        clocks = <&syscon ASPEED_CLK_APB>;
+        interrupt-controller;
+        ngpios = <8>;
+        max-ngpios = <80>;
+        bus-frequency = <12000000>;
+    };
diff --git a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
deleted file mode 100644
index be329ea4794f..000000000000
--- a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Aspeed SGPIO controller Device Tree Bindings
---------------------------------------------
-
-This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
-featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
-support the following options:
-- Support interrupt option for each input port and various interrupt
-  sensitivity option (level-high, level-low, edge-high, edge-low)
-- Support reset tolerance option for each output port
-- Directly connected to APB bus and its shift clock is from APB bus clock
-  divided by a programmable value.
-- Co-work with external signal-chained TTL components (74LV165/74LV595)
-
-Required properties:
-
-- compatible : Should be one of
-  "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
-- #gpio-cells : Should be 2, see gpio.txt
-- reg : Address and length of the register set for the device
-- gpio-controller : Marks the device node as a GPIO controller
-- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
-- interrupt-controller : Mark the GPIO controller as an interrupt-controller
-- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
-  2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
-  output. Up to 80 pins, must be a multiple of 8.
-- clocks : A phandle to the APB clock for SGPM clock division
-- bus-frequency : SGPM CLK frequency
-
-The sgpio and interrupt properties are further described in their respective
-bindings documentation:
-
-- Documentation/devicetree/bindings/gpio/gpio.txt
-- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-  Example:
-	sgpio: sgpio@1e780200 {
-		#gpio-cells = <2>;
-		compatible = "aspeed,ast2500-sgpio";
-		gpio-controller;
-		interrupts = <40>;
-		reg = <0x1e780200 0x0100>;
-		clocks = <&syscon ASPEED_CLK_APB>;
-		interrupt-controller;
-		ngpios = <8>;
-		bus-frequency = <12000000>;
-	};
-- 
2.17.1


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[PATCH v2 2/4] ARM: dts: aspeed-g6: Add SGPIO node.

[Steven Lee]

AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
with 80 pins.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index f96607b7b4e2..556ce9535c22 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -377,6 +377,38 @@
 				#interrupt-cells = <2>;
 			};
 
+			sgpiom0: sgpiom@1e780500 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpiom";
+				reg = <0x1e780500 0x100>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				max-ngpios = <128>;
+				ngpios = <128>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+				interrupt-controller;
+				bus-frequency = <12000000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sgpm1_default>;
+				status = "disabled";
+			};
+
+			sgpiom1: sgpiom@1e780600 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpiom";
+				reg = <0x1e780600 0x100>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				max-ngpios = <80>;
+				ngpios = <80>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+				interrupt-controller;
+				bus-frequency = <12000000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sgpm2_default>;
+				status = "disabled";
+			};
+
 			gpio1: gpio@1e780800 {
 				#gpio-cells = <2>;
 				gpio-controller;
-- 
2.17.1


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[PATCH v2 3/4] ARM: dts: aspeed-g5: Modify sgpio node for the enhanced sgpio driver.

[Steven Lee]

The enhanced sgpio driver has changed the compatible name to sgpiom
and reads the max number of sgpio pins that SoC supported from
max-ngpios in dts.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed-g5.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d733c1f161c1..730cbd48eedb 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -345,13 +345,14 @@
 
 			sgpio: sgpio@1e780200 {
 				#gpio-cells = <2>;
-				compatible = "aspeed,ast2500-sgpio";
+				compatible = "aspeed,ast2500-sgpiom";
 				gpio-controller;
 				interrupts = <40>;
 				reg = <0x1e780200 0x0100>;
 				clocks = <&syscon ASPEED_CLK_APB>;
 				interrupt-controller;
 				ngpios = <8>;
+				max-ngpios = <80>;
 				bus-frequency = <12000000>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_sgpm_default>;
-- 
2.17.1


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[PATCH v2 4/4] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

[Steven Lee]

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, and AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.
The patch makes the maximum gpio number *constraint of chip* comes from
the dts. The property name is max-ngpios.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 193 ++++++++++++++++++++-----------
 1 file changed, 125 insertions(+), 68 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 64e54f8c30d2..d01cdaeeada4 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -17,37 +17,28 @@
 #include <linux/spinlock.h>
 #include <linux/string.h>
 
-/*
- * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
- * slots within the clocked serial GPIO data). Since each HW GPIO is both an
- * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
- * device.
- *
- * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
- * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
- */
-#define MAX_NR_HW_SGPIO			80
-#define SGPIO_OUTPUT_OFFSET		MAX_NR_HW_SGPIO
-
 #define ASPEED_SGPIO_CTRL		0x54
 
-#define ASPEED_SGPIO_PINS_MASK		GENMASK(9, 6)
+#define ASPEED_SGPIO_PINS_MASK		GENMASK(10, 6)
 #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
 #define ASPEED_SGPIO_ENABLE		BIT(0)
 
 struct aspeed_sgpio {
 	struct gpio_chip chip;
+	struct irq_chip intc;
 	struct clk *pclk;
 	spinlock_t lock;
 	void __iomem *base;
 	int irq;
+	int max_ngpios;
 	int n_sgpio;
 };
 
 struct aspeed_sgpio_bank {
-	uint16_t    val_regs;
-	uint16_t    rdata_reg;
-	uint16_t    irq_regs;
+	u16    val_regs;
+	u16    rdata_reg;
+	u16    irq_regs;
+	u16    tolerance_regs;
 	const char  names[4][3];
 };
 
@@ -63,19 +54,29 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
 		.val_regs = 0x0000,
 		.rdata_reg = 0x0070,
 		.irq_regs = 0x0004,
+		.tolerance_regs = 0x0018,
 		.names = { "A", "B", "C", "D" },
 	},
 	{
 		.val_regs = 0x001C,
 		.rdata_reg = 0x0074,
 		.irq_regs = 0x0020,
+		.tolerance_regs = 0x0034,
 		.names = { "E", "F", "G", "H" },
 	},
 	{
 		.val_regs = 0x0038,
 		.rdata_reg = 0x0078,
 		.irq_regs = 0x003C,
-		.names = { "I", "J" },
+		.tolerance_regs = 0x0050,
+		.names = { "I", "J", "K", "L" },
+	},
+	{
+		.val_regs = 0x0090,
+		.rdata_reg = 0x007C,
+		.irq_regs = 0x0094,
+		.tolerance_regs = 0x00A8,
+		.names = { "M", "N", "O", "P" },
 	},
 };
 
@@ -87,14 +88,14 @@ enum aspeed_sgpio_reg {
 	reg_irq_type1,
 	reg_irq_type2,
 	reg_irq_status,
+	reg_tolerance,
 };
 
-#define GPIO_VAL_VALUE      0x00
-#define GPIO_IRQ_ENABLE     0x00
-#define GPIO_IRQ_TYPE0      0x04
-#define GPIO_IRQ_TYPE1      0x08
-#define GPIO_IRQ_TYPE2      0x0C
-#define GPIO_IRQ_STATUS     0x10
+#define GPIO_IRQ_OFFSET_ENABLE     0x00
+#define GPIO_IRQ_OFFSET_TYPE0      0x04
+#define GPIO_IRQ_OFFSET_TYPE1      0x08
+#define GPIO_IRQ_OFFSET_TYPE2      0x0C
+#define GPIO_IRQ_OFFSET_STATUS     0x10
 
 static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
 				     const struct aspeed_sgpio_bank *bank,
@@ -102,34 +103,37 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
 {
 	switch (reg) {
 	case reg_val:
-		return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
+		return gpio->base + bank->val_regs;
 	case reg_rdata:
 		return gpio->base + bank->rdata_reg;
 	case reg_irq_enable:
-		return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
+		return gpio->base + bank->irq_regs + GPIO_IRQ_OFFSET_ENABLE;
 	case reg_irq_type0:
-		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
+		return gpio->base + bank->irq_regs + GPIO_IRQ_OFFSET_TYPE0;
 	case reg_irq_type1:
-		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
+		return gpio->base + bank->irq_regs + GPIO_IRQ_OFFSET_TYPE1;
 	case reg_irq_type2:
-		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
+		return gpio->base + bank->irq_regs + GPIO_IRQ_OFFSET_TYPE2;
 	case reg_irq_status:
-		return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
+		return gpio->base + bank->irq_regs + GPIO_IRQ_OFFSET_STATUS;
+	case reg_tolerance:
+		return gpio->base + bank->tolerance_regs;
 	default:
 		/* acturally if code runs to here, it's an error case */
 		BUG();
 	}
 }
 
-#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
-#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
+#define GPIO_BANK(x)    ((x) >> 5)
+/* modulo 32 */
+#define GPIO_OFFSET(x)  ((x) & 0x1f)
 #define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
 
-static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
+static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, unsigned int max_ngpios)
 {
 	unsigned int bank;
 
-	bank = GPIO_BANK(offset);
+	bank = GPIO_BANK(offset % max_ngpios);
 
 	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
 	return &aspeed_sgpio_banks[bank];
@@ -139,18 +143,19 @@ static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
 		unsigned long *valid_mask, unsigned int ngpios)
 {
 	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
+	int max_ngpios = sgpio->max_ngpios;
 	int n = sgpio->n_sgpio;
-	int c = SGPIO_OUTPUT_OFFSET - n;
+	int c = max_ngpios - n;
 
-	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
+	WARN_ON(ngpios < max_ngpios * 2);
 
 	/* input GPIOs in the lower range */
 	bitmap_set(valid_mask, 0, n);
 	bitmap_clear(valid_mask, n, c);
 
-	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
-	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
-	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
+	/* output GPIOS above max_ngpios */
+	bitmap_set(valid_mask, max_ngpios, n);
+	bitmap_clear(valid_mask, max_ngpios + n, c);
 
 	return 0;
 }
@@ -161,30 +166,30 @@ static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
 	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
 	int n = sgpio->n_sgpio;
 
-	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
+	WARN_ON(ngpios < sgpio->max_ngpios * 2);
 
 	/* input GPIOs in the lower range */
 	bitmap_set(valid_mask, 0, n);
 	bitmap_clear(valid_mask, n, ngpios - n);
 }
 
-static bool aspeed_sgpio_is_input(unsigned int offset)
+static bool aspeed_sgpio_is_input(unsigned int offset, unsigned int max_ngpios)
 {
-	return offset < SGPIO_OUTPUT_OFFSET;
+	return offset < max_ngpios;
 }
 
 static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
 {
 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
-	const struct aspeed_sgpio_bank *bank = to_bank(offset);
+	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio->max_ngpios);
 	unsigned long flags;
 	enum aspeed_sgpio_reg reg;
 	int rc = 0;
 
 	spin_lock_irqsave(&gpio->lock, flags);
 
-	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
-	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
+	reg = aspeed_sgpio_is_input(offset, gpio->max_ngpios) ? reg_val : reg_rdata;
+	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset % gpio->max_ngpios));
 
 	spin_unlock_irqrestore(&gpio->lock, flags);
 
@@ -194,11 +199,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
 static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
 {
 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
-	const struct aspeed_sgpio_bank *bank = to_bank(offset);
+	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio->max_ngpios);
 	void __iomem *addr_r, *addr_w;
 	u32 reg = 0;
 
-	if (aspeed_sgpio_is_input(offset))
+	if (aspeed_sgpio_is_input(offset, gpio->max_ngpios))
 		return -EINVAL;
 
 	/* Since this is an output, read the cached value from rdata, then
@@ -209,9 +214,9 @@ static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
 	reg = ioread32(addr_r);
 
 	if (val)
-		reg |= GPIO_BIT(offset);
+		reg |= GPIO_BIT(offset % gpio->max_ngpios);
 	else
-		reg &= ~GPIO_BIT(offset);
+		reg &= ~GPIO_BIT(offset % gpio->max_ngpios);
 
 	iowrite32(reg, addr_w);
 
@@ -232,7 +237,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
 
 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
 {
-	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
+	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+
+	return aspeed_sgpio_is_input(offset, gpio->max_ngpios) ? 0 : -EINVAL;
 }
 
 static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
@@ -253,7 +260,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int v
 
 static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 {
-	return !!aspeed_sgpio_is_input(offset);
+	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+
+	return !!aspeed_sgpio_is_input(offset, gpio->max_ngpios);
 }
 
 static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
@@ -268,8 +277,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
 	WARN_ON(!internal);
 
 	*gpio = internal;
-	*bank = to_bank(*offset);
-	*bit = GPIO_BIT(*offset);
+	*bank = to_bank(*offset, internal->max_ngpios);
+	*bit = GPIO_BIT(*offset % internal->max_ngpios);
 }
 
 static void aspeed_sgpio_irq_ack(struct irq_data *d)
@@ -412,14 +421,6 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
 	chained_irq_exit(ic, desc);
 }
 
-static struct irq_chip aspeed_sgpio_irqchip = {
-	.name       = "aspeed-sgpio",
-	.irq_ack    = aspeed_sgpio_irq_ack,
-	.irq_mask   = aspeed_sgpio_irq_mask,
-	.irq_unmask = aspeed_sgpio_irq_unmask,
-	.irq_set_type   = aspeed_sgpio_set_type,
-};
-
 static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 				   struct platform_device *pdev)
 {
@@ -442,8 +443,14 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 		iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
 	}
 
+	gpio->intc.name = dev_name(&pdev->dev);
+	gpio->intc.irq_ack = aspeed_sgpio_irq_ack;
+	gpio->intc.irq_mask = aspeed_sgpio_irq_mask;
+	gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;
+	gpio->intc.irq_set_type = aspeed_sgpio_set_type;
+
 	irq = &gpio->chip.irq;
-	irq->chip = &aspeed_sgpio_irqchip;
+	irq->chip = &gpio->intc;
 	irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
 	irq->handler = handle_bad_irq;
 	irq->default_type = IRQ_TYPE_NONE;
@@ -466,9 +473,48 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 	return 0;
 }
 
+static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
+					unsigned int offset, bool enable)
+{
+	struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
+	unsigned long flags;
+	void __iomem *reg;
+	u32 val;
+
+	reg = bank_reg(gpio, to_bank(offset, gpio->max_ngpios), reg_tolerance);
+
+	spin_lock_irqsave(&gpio->lock, flags);
+
+	val = readl(reg);
+
+	if (enable)
+		val |= GPIO_BIT(offset % gpio->max_ngpios);
+	else
+		val &= ~GPIO_BIT(offset % gpio->max_ngpios);
+
+	writel(val, reg);
+
+	spin_unlock_irqrestore(&gpio->lock, flags);
+
+	return 0;
+}
+
+static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
+				   unsigned long config)
+{
+	unsigned long param = pinconf_to_config_param(config);
+	u32 arg = pinconf_to_config_argument(config);
+
+	if (param == PIN_CONFIG_PERSIST_STATE)
+		return aspeed_sgpio_reset_tolerance(chip, offset, arg);
+	else
+		return -EOPNOTSUPP;
+}
+
 static const struct of_device_id aspeed_sgpio_of_table[] = {
-	{ .compatible = "aspeed,ast2400-sgpio" },
-	{ .compatible = "aspeed,ast2500-sgpio" },
+	{ .compatible = "aspeed,ast2400-sgpiom" },
+	{ .compatible = "aspeed,ast2500-sgpiom" },
+	{ .compatible = "aspeed,ast2600-sgpiom" },
 	{}
 };
 
@@ -476,8 +522,8 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
 
 static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 {
+	u32 nr_gpios, sgpio_freq, sgpio_clk_div, max_ngpios;
 	struct aspeed_sgpio *gpio;
-	u32 nr_gpios, sgpio_freq, sgpio_clk_div;
 	int rc;
 	unsigned long apb_freq;
 
@@ -489,13 +535,24 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	if (IS_ERR(gpio->base))
 		return PTR_ERR(gpio->base);
 
+	rc = of_property_read_u32(pdev->dev.of_node, "max-ngpios", &max_ngpios);
+	if (rc < 0) {
+		dev_err(&pdev->dev, "Could not read max-ngpios property\n");
+		return -EINVAL;
+	}
+	gpio->max_ngpios = max_ngpios;
+
 	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Could not read ngpios property\n");
 		return -EINVAL;
-	} else if (nr_gpios > MAX_NR_HW_SGPIO) {
+	} else if (nr_gpios % 8) {
+		dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
+			nr_gpios);
+		return -EINVAL;
+	} else if (nr_gpios > gpio->max_ngpios) {
 		dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
-			MAX_NR_HW_SGPIO, nr_gpios);
+			gpio->max_ngpios, nr_gpios);
 		return -EINVAL;
 	}
 	gpio->n_sgpio = nr_gpios;
@@ -539,7 +596,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	spin_lock_init(&gpio->lock);
 
 	gpio->chip.parent = &pdev->dev;
-	gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2;
+	gpio->chip.ngpio = gpio->max_ngpios * 2;
 	gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
 	gpio->chip.direction_input = aspeed_sgpio_dir_in;
 	gpio->chip.direction_output = aspeed_sgpio_dir_out;
@@ -548,7 +605,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	gpio->chip.free = NULL;
 	gpio->chip.get = aspeed_sgpio_get;
 	gpio->chip.set = aspeed_sgpio_set;
-	gpio->chip.set_config = NULL;
+	gpio->chip.set_config = aspeed_sgpio_set_config;
 	gpio->chip.label = dev_name(&pdev->dev);
 	gpio->chip.base = -1;
 
-- 
2.17.1


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Re: [PATCH v2 0/4] ASPEED sgpio driver enhancement.

[Andrew Jeffery]

Hi Steven,

On Thu, 27 May 2021, at 10:24, Steven Lee wrote:
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
> supports up to 80 pins.
> In the current driver design, the max number of sgpio pins is hardcoded
> in macro MAX_NR_HW_SGPIO and the value is 80.
> 
> For supporting sgpio master interfaces of AST2600 SoC, the patch series
> contains the following enhancement:
> - Convert txt dt-bindings to yaml.
> - Update aspeed dtsi to support the enhanced sgpio.
> - Get the max number of sgpio that SoC supported from dts.
> - Support muiltiple SGPIO master interfaces.
> - Support up to 128 pins.
> 
> Changes from v1:
> * Fix yaml format issues.
> * Fix issues reported by kernel test robot.
> 
> Please help to review.

I think it's worth leaving a little more time between sending series.

I've just sent a bunch of reviews on v1.

Cheers,

Andrew

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Re: [PATCH v2 0/4] ASPEED sgpio driver enhancement.

[Steven Lee]

The 05/27/2021 09:41, Andrew Jeffery wrote:
> Hi Steven,
> 
> On Thu, 27 May 2021, at 10:24, Steven Lee wrote:
> > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
> > supports up to 80 pins.
> > In the current driver design, the max number of sgpio pins is hardcoded
> > in macro MAX_NR_HW_SGPIO and the value is 80.
> > 
> > For supporting sgpio master interfaces of AST2600 SoC, the patch series
> > contains the following enhancement:
> > - Convert txt dt-bindings to yaml.
> > - Update aspeed dtsi to support the enhanced sgpio.
> > - Get the max number of sgpio that SoC supported from dts.
> > - Support muiltiple SGPIO master interfaces.
> > - Support up to 128 pins.
> > 
> > Changes from v1:
> > * Fix yaml format issues.
> > * Fix issues reported by kernel test robot.
> > 
> > Please help to review.
> 
> I think it's worth leaving a little more time between sending series.
> 
> I've just sent a bunch of reviews on v1.
> 

I am worried about the patch series may be drop by reviewers due to
the report of kernel test robot.

Regardless, thanks for the comment in v1 patch series.

Steven

> Cheers,
> 
> Andrew

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Re: [PATCH v2 1/4] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.

[Linus Walleij]

On Thu, May 27, 2021 at 2:55 AM Steven Lee <steven_lee@aspeedtech.com> wrote:

> SGPIO bindings should be converted as yaml format.
> In addition to the file conversion, a new property max-ngpios is
> added in the yaml file as well.
> The new property is required by the enhanced sgpio driver for
> making the configuration of the max number of gpio pins more flexible.
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
(...)
> +  max-ngpios:
> +    description:
> +      represents the number of actual hardware-supported GPIOs (ie,
> +      slots within the clocked serial GPIO data). Since each HW GPIO is both an
> +      input and an output, we provide max_ngpios * 2 lines on our gpiochip
> +      device. We also use it to define the split between the inputs and
> +      outputs; the inputs start at line 0, the outputs start at max_ngpios.
> +    minimum: 0
> +    maximum: 128

Why can this not be derived from the compatible value?

Normally there should be one compatible per hardware variant
of the block. And this should be aligned with that, should it not?

If this is not the case, maybe more detailed compatible strings
are needed, maybe double compatibles with compatible per
family and SoC?

Yours,
Linus Walleij

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Re: [PATCH v2 1/4] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.

[Steven Lee]

The 05/28/2021 07:51, Linus Walleij wrote:
> On Thu, May 27, 2021 at 2:55 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
> 
> > SGPIO bindings should be converted as yaml format.
> > In addition to the file conversion, a new property max-ngpios is
> > added in the yaml file as well.
> > The new property is required by the enhanced sgpio driver for
> > making the configuration of the max number of gpio pins more flexible.
> >
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> (...)
> > +  max-ngpios:
> > +    description:
> > +      represents the number of actual hardware-supported GPIOs (ie,
> > +      slots within the clocked serial GPIO data). Since each HW GPIO is both an
> > +      input and an output, we provide max_ngpios * 2 lines on our gpiochip
> > +      device. We also use it to define the split between the inputs and
> > +      outputs; the inputs start at line 0, the outputs start at max_ngpios.
> > +    minimum: 0
> > +    maximum: 128
> 
> Why can this not be derived from the compatible value?
> 
> Normally there should be one compatible per hardware variant
> of the block. And this should be aligned with that, should it not?
> 
> If this is not the case, maybe more detailed compatible strings
> are needed, maybe double compatibles with compatible per
> family and SoC?
> 

Thanks for your suggestion.
I add max-ngpios in dt-bindings as there is ngpios defined in
dt-bindings, users can get the both max-ngpios and ngpios information
from dtsi without digging sgpio driver.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/aspeed-g5.dtsi#n354

If adding more detailed compatibles is better, I will add them to sgpio driver
in V3 patch and remove max-ngpios from dt-bindings.

Since AST2600 has 2 sgpio controller one with 128 pins and another one with 80 pins.
For supporting max-ngpios in compatibles, 2 platform data for each
ast2600 sgpio controller as follows are necessary.

```
static const struct aspeed_sgpio_pdata ast2600_sgpiom1_pdata = {
        .max_ngpios = 128;
};
static const struct aspeed_sgpio_pdata ast2600_sgpiom2_pdata = {
        .max_ngpios = 80;
};

{ .compatible = "aspeed,ast2500-sgpio" , .data = &ast2400_sgpio_pdata, },
{ .compatible = "aspeed,ast2600-sgpiom1", .data = &ast2600_sgpiom1_pdata, },
{ .compatible = "aspeed,ast2600-sgpiom2", .data = &ast2600_sgpiom2_pdata, },
```

Thanks,
Steven

> Yours,
> Linus Walleij

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Re: [PATCH v2 1/4] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.

[Linus Walleij]

On Fri, May 28, 2021 at 6:10 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
> The 05/28/2021 07:51, Linus Walleij wrote:
> > On Thu, May 27, 2021 at 2:55 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
> >
> > > +  max-ngpios:
> > > +    description:
> > > +      represents the number of actual hardware-supported GPIOs (ie,
> > > +      slots within the clocked serial GPIO data). Since each HW GPIO is both an
> > > +      input and an output, we provide max_ngpios * 2 lines on our gpiochip
> > > +      device. We also use it to define the split between the inputs and
> > > +      outputs; the inputs start at line 0, the outputs start at max_ngpios.
> > > +    minimum: 0
> > > +    maximum: 128
> >
> > Why can this not be derived from the compatible value?
> >
> > Normally there should be one compatible per hardware variant
> > of the block. And this should be aligned with that, should it not?
> >
> > If this is not the case, maybe more detailed compatible strings
> > are needed, maybe double compatibles with compatible per
> > family and SoC?
> >
>
> Thanks for your suggestion.
> I add max-ngpios in dt-bindings as there is ngpios defined in
> dt-bindings, users can get the both max-ngpios and ngpios information
> from dtsi without digging sgpio driver.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/aspeed-g5.dtsi#n354
>
> If adding more detailed compatibles is better, I will add them to sgpio driver
> in V3 patch and remove max-ngpios from dt-bindings.
>
> Since AST2600 has 2 sgpio controller one with 128 pins and another one with 80 pins.
> For supporting max-ngpios in compatibles, 2 platform data for each
> ast2600 sgpio controller as follows are necessary.
>
> ```
> static const struct aspeed_sgpio_pdata ast2600_sgpiom1_pdata = {
>         .max_ngpios = 128;
> };
> static const struct aspeed_sgpio_pdata ast2600_sgpiom2_pdata = {
>         .max_ngpios = 80;
> };
>
> { .compatible = "aspeed,ast2500-sgpio" , .data = &ast2400_sgpio_pdata, },
> { .compatible = "aspeed,ast2600-sgpiom1", .data = &ast2600_sgpiom1_pdata, },
> { .compatible = "aspeed,ast2600-sgpiom2", .data = &ast2600_sgpiom2_pdata, },

There is a soft border between two IP blocks being "compatible"
and parameterized and two IP blocks being different and having
unique compatibles.

For example we know for sure we don't use different compatibles
because of how interrupt lines or DMA channels are connected.

So if this is an external thing, outside of the IP itself, I might back
off on this and say it shall be a parameter.

But max-ngpios? It is confusingly similar to ngpios.

So we need to think about this name.

Something like gpio-hardware-slots or something else that
really describe what this is.

Does this always strictly follow ngpios so that the number
of gpio slots == ngpios * 2? In that case only put ngpios into
the device tree and multiply by 2 in the driver, because ngpios
is exactly for this: parameterizing hardware limitations.

Yours,
Linus Walleij

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Re: [PATCH v2 1/4] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.

[Steven Lee]

The 05/28/2021 16:35, Linus Walleij wrote:
> On Fri, May 28, 2021 at 6:10 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
> > The 05/28/2021 07:51, Linus Walleij wrote:
> > > On Thu, May 27, 2021 at 2:55 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
> > >
> > > > +  max-ngpios:
> > > > +    description:
> > > > +      represents the number of actual hardware-supported GPIOs (ie,
> > > > +      slots within the clocked serial GPIO data). Since each HW GPIO is both an
> > > > +      input and an output, we provide max_ngpios * 2 lines on our gpiochip
> > > > +      device. We also use it to define the split between the inputs and
> > > > +      outputs; the inputs start at line 0, the outputs start at max_ngpios.
> > > > +    minimum: 0
> > > > +    maximum: 128
> > >
> > > Why can this not be derived from the compatible value?
> > >
> > > Normally there should be one compatible per hardware variant
> > > of the block. And this should be aligned with that, should it not?
> > >
> > > If this is not the case, maybe more detailed compatible strings
> > > are needed, maybe double compatibles with compatible per
> > > family and SoC?
> > >
> >
> > Thanks for your suggestion.
> > I add max-ngpios in dt-bindings as there is ngpios defined in
> > dt-bindings, users can get the both max-ngpios and ngpios information
> > from dtsi without digging sgpio driver.
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/aspeed-g5.dtsi#n354
> >
> > If adding more detailed compatibles is better, I will add them to sgpio driver
> > in V3 patch and remove max-ngpios from dt-bindings.
> >
> > Since AST2600 has 2 sgpio controller one with 128 pins and another one with 80 pins.
> > For supporting max-ngpios in compatibles, 2 platform data for each
> > ast2600 sgpio controller as follows are necessary.
> >
> > ```
> > static const struct aspeed_sgpio_pdata ast2600_sgpiom1_pdata = {
> >         .max_ngpios = 128;
> > };
> > static const struct aspeed_sgpio_pdata ast2600_sgpiom2_pdata = {
> >         .max_ngpios = 80;
> > };
> >
> > { .compatible = "aspeed,ast2500-sgpio" , .data = &ast2400_sgpio_pdata, },
> > { .compatible = "aspeed,ast2600-sgpiom1", .data = &ast2600_sgpiom1_pdata, },
> > { .compatible = "aspeed,ast2600-sgpiom2", .data = &ast2600_sgpiom2_pdata, },
> 
> There is a soft border between two IP blocks being "compatible"
> and parameterized and two IP blocks being different and having
> unique compatibles.
> 
> For example we know for sure we don't use different compatibles
> because of how interrupt lines or DMA channels are connected.
> 

Thanks for sharing the knowledge and examples.

> So if this is an external thing, outside of the IP itself, I might back
> off on this and say it shall be a parameter.
> 
> But max-ngpios? It is confusingly similar to ngpios.
> 
> So we need to think about this name.
> 
> Something like gpio-hardware-slots or something else that
> really describe what this is.
> 
> Does this always strictly follow ngpios so that the number
> of gpio slots == ngpios * 2? In that case only put ngpios into
> the device tree and multiply by 2 in the driver, because ngpios
> is exactly for this: parameterizing hardware limitations.
> 

The parameter max-ngpios is the maxmum number of gpio pins that SoC supported,
ngpios is the maximum number of gpio pins that sgpio devices(e.g. sgpio cards) supported.

For instance, a sgpio card that supports 64 gpio pins which is connected to
ast2600evb sgpio master interface 2. The dts file should be configured as follows.

```
max-ngpios = <80>
ngpios = <64>

```

About the parameter naming, I was wondering if 'ngpios-of-sgpiom' is more clear
than max-ngpios as it is the maximum number of gpio pins that sgpio master
interfaces supported.

> Yours,
> Linus Walleij

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Re: [PATCH v2 1/4] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.

[Linus Walleij]

On Mon, May 31, 2021 at 7:23 AM Steven Lee <steven_lee@aspeedtech.com> wrote:

> The parameter max-ngpios is the maxmum number of gpio pins that SoC supported,
> ngpios is the maximum number of gpio pins that sgpio devices(e.g. sgpio cards) supported.

When you put it like that you really make it sound like you already
know, just looking at the compatible string, what max-ngpios is?

I.e. do you know for these three:

aspeed,ast2400-sgpiom
aspeed,ast2500-sgpiom
aspeed,ast2600-sgpiom

the unique number of slots for each? A 1-to-1 correspondance?

Then just add code to set this value from looking at the compatible
in the driver. You can write some text in description in these bindings
about how many slots each SoC has but there is no need to add any
extra parameter if you already know this from the SoC.

Yours,
Linus Walleij

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Re: [PATCH v2 1/4] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.

[Rob Herring]

On Thu, May 27, 2021 at 08:54:50AM +0800, Steven Lee wrote:
> SGPIO bindings should be converted as yaml format.
> In addition to the file conversion, a new property max-ngpios is
> added in the yaml file as well.
> The new property is required by the enhanced sgpio driver for
> making the configuration of the max number of gpio pins more flexible.

The rest of the binding looks fine. Make this property a separate patch 
if you don't end up dropping it.

> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  .../bindings/gpio/aspeed,sgpio.yaml           | 91 +++++++++++++++++++
>  .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ----------
>  2 files changed, 91 insertions(+), 46 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
>  delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> new file mode 100644
> index 000000000000..02eb0c5023e9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> @@ -0,0 +1,91 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed SGPIO controller
> +
> +maintainers:
> +  - Andrew Jeffery <andrew@aj.id.au>
> +
> +description:
> +  This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
> +  AST2600 have two sgpio master one with 128 pins another one with 80 pins,
> +  AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
> +  GPIO pins can be programmed to support the following options
> +  - Support interrupt option for each input port and various interrupt
> +    sensitivity option (level-high, level-low, edge-high, edge-low)
> +  - Support reset tolerance option for each output port
> +  - Directly connected to APB bus and its shift clock is from APB bus clock
> +    divided by a programmable value.
> +  - Co-work with external signal-chained TTL components (74LV165/74LV595)
> +
> +properties:
> +  compatible:
> +    enum:
> +      - aspeed,ast2400-sgpiom
> +      - aspeed,ast2500-sgpiom
> +      - aspeed,ast2600-sgpiom
> +
> +  reg:
> +    maxItems: 1
> +
> +  gpio-controller: true
> +
> +  '#gpio-cells':
> +    const: 2
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  clocks:
> +    maxItems: 1
> +
> +  ngpios:
> +    minimum: 0
> +    maximum: 128
> +
> +  max-ngpios:
> +    description:
> +      represents the number of actual hardware-supported GPIOs (ie,
> +      slots within the clocked serial GPIO data). Since each HW GPIO is both an
> +      input and an output, we provide max_ngpios * 2 lines on our gpiochip
> +      device. We also use it to define the split between the inputs and
> +      outputs; the inputs start at line 0, the outputs start at max_ngpios.
> +    minimum: 0
> +    maximum: 128
> +
> +  bus-frequency: true
> +
> +required:
> +  - compatible
> +  - reg
> +  - gpio-controller
> +  - '#gpio-cells'
> +  - interrupts
> +  - interrupt-controller
> +  - ngpios
> +  - max-ngpios
> +  - clocks
> +  - bus-frequency
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/aspeed-clock.h>
> +    sgpio: sgpio@1e780200 {
> +        #gpio-cells = <2>;
> +        compatible = "aspeed,ast2500-sgpiom";
> +        gpio-controller;
> +        interrupts = <40>;
> +        reg = <0x1e780200 0x0100>;
> +        clocks = <&syscon ASPEED_CLK_APB>;
> +        interrupt-controller;
> +        ngpios = <8>;
> +        max-ngpios = <80>;
> +        bus-frequency = <12000000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> deleted file mode 100644
> index be329ea4794f..000000000000
> --- a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> +++ /dev/null
> @@ -1,46 +0,0 @@
> -Aspeed SGPIO controller Device Tree Bindings
> ---------------------------------------------
> -
> -This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
> -featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
> -support the following options:
> -- Support interrupt option for each input port and various interrupt
> -  sensitivity option (level-high, level-low, edge-high, edge-low)
> -- Support reset tolerance option for each output port
> -- Directly connected to APB bus and its shift clock is from APB bus clock
> -  divided by a programmable value.
> -- Co-work with external signal-chained TTL components (74LV165/74LV595)
> -
> -Required properties:
> -
> -- compatible : Should be one of
> -  "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
> -- #gpio-cells : Should be 2, see gpio.txt
> -- reg : Address and length of the register set for the device
> -- gpio-controller : Marks the device node as a GPIO controller
> -- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
> -- interrupt-controller : Mark the GPIO controller as an interrupt-controller
> -- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
> -  2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
> -  output. Up to 80 pins, must be a multiple of 8.
> -- clocks : A phandle to the APB clock for SGPM clock division
> -- bus-frequency : SGPM CLK frequency
> -
> -The sgpio and interrupt properties are further described in their respective
> -bindings documentation:
> -
> -- Documentation/devicetree/bindings/gpio/gpio.txt
> -- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
> -
> -  Example:
> -	sgpio: sgpio@1e780200 {
> -		#gpio-cells = <2>;
> -		compatible = "aspeed,ast2500-sgpio";
> -		gpio-controller;
> -		interrupts = <40>;
> -		reg = <0x1e780200 0x0100>;
> -		clocks = <&syscon ASPEED_CLK_APB>;
> -		interrupt-controller;
> -		ngpios = <8>;
> -		bus-frequency = <12000000>;
> -	};
> -- 
> 2.17.1

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