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Fri, 28 May 2021 07:05:12 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 28 May 2021 07:05:12 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Fri, 28 May 2021 07:05:12 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14SC5BbN130682; Fri, 28 May 2021 07:05:11 -0500 Date: Fri, 28 May 2021 17:35:10 +0530 From: Pratyush Yadav To: CC: Mark Brown , Miquel Raynal , Vignesh Raghavendra , Boris Brezillon , , Alexandre Torgue , , , , , Subject: Re: [PATCH v3 3/3] mtd: spinand: add SPI-NAND MTD resume handler Message-ID: <20210528120508.f6viglv3gkzgweqq@ti.com> References: <20210527161252.16620-1-patrice.chotard@foss.st.com> <20210527161252.16620-4-patrice.chotard@foss.st.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210527161252.16620-4-patrice.chotard@foss.st.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210528_050523_231975_7EE91F90 X-CRM114-Status: GOOD ( 24.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 27/05/21 06:12PM, patrice.chotard@foss.st.com wrote: > From: Patrice Chotard > > After power up, all SPI NAND's blocks are locked. Only read operations > are allowed, write and erase operations are forbidden. > The SPI NAND framework unlocks all the blocks during its initialization. > > During a standby low power, the memory is powered down, losing its > configuration. > During the resume, the QSPI driver state is restored but the SPI NAND > framework does not reconfigured the memory. > > This patch adds SPI-NAND MTD PM handlers for resume ops. > SPI NAND resume op re-initializes SPI NAND flash to its probed state. > > Signed-off-by: Christophe Kerello > Signed-off-by: Patrice Chotard > --- > Changes in v3: > - Add spinand_read_cfg() call to repopulate cache > > Changes in v2: > - Add helper spinand_block_unlock(). > - Add spinand_ecc_enable() call. > - Remove some dev_err(). > - Fix commit's title and message. > > drivers/mtd/nand/spi/core.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c > index 1f699ad84f1b..e3fcbcf381c3 100644 > --- a/drivers/mtd/nand/spi/core.c > +++ b/drivers/mtd/nand/spi/core.c > @@ -1099,6 +1099,38 @@ static int spinand_block_unlock(struct spinand_device *spinand) > return ret; > } > > +static void spinand_mtd_resume(struct mtd_info *mtd) > +{ > + struct spinand_device *spinand = mtd_to_spinand(mtd); > + int ret; > + > + ret = spinand_reset_op(spinand); > + if (ret) > + return; > + > + ret = spinand_read_cfg(spinand); > + if (ret) > + return; > + > + ret = spinand_init_quad_enable(spinand); > + if (ret) > + return; > + > + ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); > + if (ret) > + return; > + > + ret = spinand_manufacturer_init(spinand); > + if (ret) > + return; > + > + ret = spinand_block_unlock(spinand); > + if (ret) > + return; > + > + spinand_ecc_enable(spinand, false); > +} > + I don't think you quite get what me and Miquel are suggesting. The helper should call all these functions like read_cfg() quad_enable(), etc. So it should look something like: int spinand_init_flash() { ret = spinand_read_cfg(spinand); if (ret) return; ret = spinand_init_quad_enable(spinand); if (ret) return; ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); if (ret) return; ret = spinand_manufacturer_init(spinand); if (ret) return; ret = spinand_block_unlock(spinand); if (ret) return; spinand_ecc_enable(spinand, false); } Then spinand_mtd_resume should look something like: int spinand_mtd_resume() { ret = spinand_reset_op(spinand); if (ret) return; return spinand_init_flash(); } And spinand_init() should look something like: int spinand_init() { ... spinand->oobbuf = ... spinand_init_flash(); spinand_create_dirmaps(); ... } > static int spinand_init(struct spinand_device *spinand) > { > struct device *dev = &spinand->spimem->spi->dev; > @@ -1186,6 +1218,7 @@ static int spinand_init(struct spinand_device *spinand) > mtd->_block_isreserved = spinand_mtd_block_isreserved; > mtd->_erase = spinand_mtd_erase; > mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; > + mtd->_resume = spinand_mtd_resume; > > if (nand->ecc.engine) { > ret = mtd_ooblayout_count_freebytes(mtd); > -- > 2.17.1 -- Regards, Pratyush Yadav Texas Instruments Inc. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel