From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA6ADC47082 for ; Mon, 7 Jun 2021 10:13:38 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96DDC610C7 for ; Mon, 7 Jun 2021 10:13:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 96DDC610C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mZ2xnYSDm7qQxFRnppu+hGCVpNBAiVRENXcPknVS6TA=; b=HuHHCr1iy47drF QtrE/0CG3ZXuSZxJ3aKKPpVdARlqzT1z3uAo9o0jXl4ABoEO80Yw1JI9+IqoNM9t0O6R35hllVNzS sqKkd6fIRV8zpm5geb5Hbh2MZdyfk2la6xSmQUXIGtG4/DRNzi9Rfg8pTtpv8eTWSAtqhDo3cxhIn TaTv+DyvGWkK8xig9SsQPWior9X3+znRBl2FiZvF7RCrYcgROoxseNt1EbVnkR3/SAas5K/F/Yf7/ LsblbWfEKKaiXvNWhxzUjTYD+ZcJzBE2jKA3MNEX19fm6Hghi2XVaOA2SXxmVe2ovoGiIUz/Jk3Up JGpzWtZwg+NGd9Jc6fZg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqCE5-002oea-DF; Mon, 07 Jun 2021 10:11:21 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqBqP-002hD1-Pz for linux-arm-kernel@lists.infradead.org; Mon, 07 Jun 2021 09:46:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8578311D4; Mon, 7 Jun 2021 02:46:53 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 84A083F719; Mon, 7 Jun 2021 02:46:52 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org, will@kernel.org Cc: catalin.marinas@arm.com, james.morse@arm.com, joey.gouly@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [PATCH v4 08/20] arm64: entry: organise entry handlers consistently Date: Mon, 7 Jun 2021 10:46:12 +0100 Message-Id: <20210607094624.34689-9-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210607094624.34689-1-mark.rutland@arm.com> References: <20210607094624.34689-1-mark.rutland@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210607_024653_961361_5267C2A4 X-CRM114-Status: GOOD ( 12.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In entry.S we have two comments which distinguish EL0 and EL1 exception handlers, but the code isn't actually laid out to match, and there are a few other inconsistencies that would be good to clear up. This patch organizes the entry handers consistently: * The handlers are laid out in order of the vectors, to make them easier to navigate. * The inconsistently-applied alignment is removed * The handlers are consistently marked with SYM_CODE_START_LOCAL() rather than SYM_CODE_START_LOCAL_NOALIGN(), giving them the same default alignment as other assembly code snippets. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Acked-by: Catalin Marinas Acked-by: Marc Zyngier Reviewed-by: Joey Gouly Cc: James Morse Cc: Will Deacon --- arch/arm64/kernel/entry.S | 78 ++++++++++++++++++++++------------------------- 1 file changed, 36 insertions(+), 42 deletions(-) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 8eb3a0a51413..ed7c55d57afe 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -607,65 +607,88 @@ SYM_CODE_END(el1_error_invalid) /* * EL1 mode handlers. */ - .align 6 -SYM_CODE_START_LOCAL_NOALIGN(el1_sync) +SYM_CODE_START_LOCAL(el1_sync) kernel_entry 1 mov x0, sp bl el1_sync_handler kernel_exit 1 SYM_CODE_END(el1_sync) - .align 6 -SYM_CODE_START_LOCAL_NOALIGN(el1_irq) +SYM_CODE_START_LOCAL(el1_irq) kernel_entry 1 mov x0, sp bl el1_irq_handler kernel_exit 1 SYM_CODE_END(el1_irq) -SYM_CODE_START_LOCAL_NOALIGN(el1_fiq) +SYM_CODE_START_LOCAL(el1_fiq) kernel_entry 1 mov x0, sp bl el1_fiq_handler kernel_exit 1 SYM_CODE_END(el1_fiq) +SYM_CODE_START_LOCAL(el1_error) + kernel_entry 1 + mov x0, sp + bl el1_error_handler + kernel_exit 1 +SYM_CODE_END(el1_error) + /* * EL0 mode handlers. */ - .align 6 -SYM_CODE_START_LOCAL_NOALIGN(el0_sync) +SYM_CODE_START_LOCAL(el0_sync) kernel_entry 0 mov x0, sp bl el0_sync_handler b ret_to_user SYM_CODE_END(el0_sync) +SYM_CODE_START_LOCAL(el0_irq) + kernel_entry 0 + mov x0, sp + bl el0_irq_handler + b ret_to_user +SYM_CODE_END(el0_irq) + +SYM_CODE_START_LOCAL(el0_fiq) + kernel_entry 0 + mov x0, sp + bl el0_fiq_handler + b ret_to_user +SYM_CODE_END(el0_fiq) + +SYM_CODE_START_LOCAL(el0_error) + kernel_entry 0 + mov x0, sp + bl el0_error_handler + b ret_to_user +SYM_CODE_END(el0_error) + #ifdef CONFIG_COMPAT - .align 6 -SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat) +SYM_CODE_START_LOCAL(el0_sync_compat) kernel_entry 0, 32 mov x0, sp bl el0_sync_compat_handler b ret_to_user SYM_CODE_END(el0_sync_compat) - .align 6 -SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat) +SYM_CODE_START_LOCAL(el0_irq_compat) kernel_entry 0, 32 mov x0, sp bl el0_irq_compat_handler b ret_to_user SYM_CODE_END(el0_irq_compat) -SYM_CODE_START_LOCAL_NOALIGN(el0_fiq_compat) +SYM_CODE_START_LOCAL(el0_fiq_compat) kernel_entry 0, 32 mov x0, sp bl el0_fiq_compat_handler b ret_to_user SYM_CODE_END(el0_fiq_compat) -SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat) +SYM_CODE_START_LOCAL(el0_error_compat) kernel_entry 0, 32 mov x0, sp bl el0_error_compat_handler @@ -673,35 +696,6 @@ SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat) SYM_CODE_END(el0_error_compat) #endif - .align 6 -SYM_CODE_START_LOCAL_NOALIGN(el0_irq) - kernel_entry 0 - mov x0, sp - bl el0_irq_handler - b ret_to_user -SYM_CODE_END(el0_irq) - -SYM_CODE_START_LOCAL_NOALIGN(el0_fiq) - kernel_entry 0 - mov x0, sp - bl el0_fiq_handler - b ret_to_user -SYM_CODE_END(el0_fiq) - -SYM_CODE_START_LOCAL(el1_error) - kernel_entry 1 - mov x0, sp - bl el1_error_handler - kernel_exit 1 -SYM_CODE_END(el1_error) - -SYM_CODE_START_LOCAL(el0_error) - kernel_entry 0 - mov x0, sp - bl el0_error_handler - b ret_to_user -SYM_CODE_END(el0_error) - /* * "slow" syscall return path. */ -- 2.11.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel