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Mon, 7 Jun 2021 09:22:58 -0400 (EDT) Date: Mon, 7 Jun 2021 15:22:55 +0200 From: Maxime Ripard To: Andre Przywara Cc: Chen-Yu Tsai , Jernej Skrabec , Rob Herring , Icenowy Zheng , Samuel Holland , Ondrej Jirman , linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , Vinod Koul , linux-phy@lists.infradead.org, linux-usb@vger.kernel.org Subject: Re: [PATCH v6 12/17] phy: sun4i-usb: Introduce port2 SIDDQ quirk Message-ID: <20210607132255.7fa75a7k7ud2g7ux@gilmour> References: <20210519104152.21119-1-andre.przywara@arm.com> <20210519104152.21119-13-andre.przywara@arm.com> <20210524115946.jwsasjbr3biyixhz@gilmour> <20210525122901.778bfccd@slackpad.fritz.box> MIME-Version: 1.0 In-Reply-To: <20210525122901.778bfccd@slackpad.fritz.box> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210607_062307_297472_2D8FBEFF X-CRM114-Status: GOOD ( 32.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============8189266480524893021==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============8189266480524893021== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="y2gxgfnqjc5ew5rx" Content-Disposition: inline --y2gxgfnqjc5ew5rx Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Tue, May 25, 2021 at 12:29:01PM +0100, Andre Przywara wrote: > On Mon, 24 May 2021 13:59:46 +0200 > Maxime Ripard wrote: >=20 > Hi Maxime, >=20 > > On Wed, May 19, 2021 at 11:41:47AM +0100, Andre Przywara wrote: > > > At least the Allwinner H616 SoC requires a weird quirk to make most > > > USB PHYs work: Only port2 works out of the box, but all other ports > > > need some help from this port2 to work correctly: The CLK_BUS_PHY2 and > > > RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in > > > the PMU PHY control register needs to be cleared. For this register to > > > be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask .... > > >=20 > > > Instead of disguising this as some generic feature, do exactly that > > > in our PHY init: > > > If the quirk bit is set, and we initialise a PHY other than PHY2, ung= ate > > > this one special clock, and clear the SIDDQ bit. We can pull in the > > > other required clocks via the DT. > > >=20 > > > Signed-off-by: Andre Przywara =20 > >=20 > > What is this SIDDQ bit doing exactly? >=20 > I probably know as much as you do, but as Jernej pointed out, in some > Rockchip code it's indeed documented as some analogue PHY supply switch: > ($ git grep -i siddq drivers/phy/rockchip) >=20 > In fact we had this pin/bit for ages, it was just hidden as BIT(1) in > our infamous PMU_UNK1 register. Patch 10/17 drags that into the light. Ok > > I guess we could also expose this using a power-domain if it's relevant? >=20 > Mmmh, interesting idea. So are you thinking about registering a genpd > provider in sun4i_usb_phy_probe(), then having a power-domains property > in the ehci/ohci nodes, pointing to the PHY node? And if yes, should > the provider be a subnode of the USB PHY node, with a separate > compatible? That sounds a bit more involved, but would have the > advantage of allowing us to specify the resets and clocks from PHY2 > there, and would look a bit cleaner than hacking them into the > other EHCI/OHCI nodes. I'm not sure we need a separate device node, we could just register the phy driver as a genpd provider, and then with an arg (so with of_genpd_add_provider_onecell?) the index of the USB controller we want to power up. > I would not touch the existing SoCs (even though it seems to apply to > them as well, just not in the exact same way), but I can give it a > try for the H616. It seems like the other SIDDQ bits (in the other > PHYs) are still needed for operation, but the PD provide could actually > take care of this as well. >=20 > Does that make sense or is this a bit over the top for just clearing an > extra bit? Using what I described above should be fairly simple, so if we can fit in an available and relevant abstraction, yeah, I guess :) Maxime --y2gxgfnqjc5ew5rx Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYL4drwAKCRDj7w1vZxhR xd7TAQDncN/zcz+Z9eSgAJaMRWNdzFFjpQWl9G5zj8Ywa1FdIAEAqsVgmYFPss9l yFRreCSeCDL8U8Q4q9q5CcNgKG6geQ0= =WN4y -----END PGP SIGNATURE----- --y2gxgfnqjc5ew5rx-- --===============8189266480524893021== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============8189266480524893021==--