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Tue, 15 Jun 2021 10:35:13 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 25F5A613FA; Tue, 15 Jun 2021 10:35:07 +0000 (UTC) Date: Tue, 15 Jun 2021 11:35:04 +0100 From: Catalin Marinas To: Yu Zhao Cc: Jia He , Mark Rutland , Will Deacon , Marc Zyngier , Suzuki Poulose , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm64: mm: fix warning in arch_faults_on_old_pte() Message-ID: <20210615103504.GD26027@arm.com> References: <20210613214728.1695340-1-yuzhao@google.com> <20210614170727.GG30667@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210615_113511_729396_A835556A X-CRM114-Status: GOOD ( 27.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 14, 2021 at 12:35:06PM -0600, Yu Zhao wrote: > On Mon, Jun 14, 2021 at 11:07 AM Catalin Marinas > wrote: > > On Sun, Jun 13, 2021 at 03:47:28PM -0600, Yu Zhao wrote: > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > > index efed2830d141..afdb6e0336ed 100644 > > > --- a/arch/arm64/kernel/cpufeature.c > > > +++ b/arch/arm64/kernel/cpufeature.c > > > @@ -1566,6 +1566,14 @@ static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, > > > return true; > > > } > > > > > > +static void cpu_enable_hw_af(struct arm64_cpu_capabilities const *cap) > > > +{ > > > + if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { > > > + u64 val = read_sysreg(tcr_el1); > > > + > > > + write_sysreg(val | TCR_HA, tcr_el1); > > > + } > > > +} > > > > This needs an isb(); local_flush_tlb_all() since this bit may be cached > > in the TLB. See how we did it in __cpu_enable_hw_dbm(). > > Thanks. I'll add it. (I omitted it since I saw it as a best effort, > not correctness related.) The TLBs would eventually be flushed but a local TLBI during boot doesn't hurt performance, so I'd rather have it. > > Alternatively you could leave the current TCR_AF bit setting as is (in > > proc.S) and only add an arm64_features[] entry for AF together with the > > arch_faults_on_old_pte() change but without any enable function. > > > > I'm not sure we have mixed CPUs where only some of them support AF to > > benefit from this. > > Can we mix CPU versions? For example, can we have A75 (v8.2 with > AFDBM) + A53 (v8 w/o AFDBM) configuration? My understanding is that we > can't. But I have not been able to find any confirmation on arm.com. Oh, don't underestimate the hardware vendors ;). But if they do, with this patch they just lose the AF benefits which I don't really mind (together with other 8.2 features which are not present in 8.0). -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel