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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=VfQdAQ7uIcnnol8WP3MAJ1Qz658s3J1UAqg2ZESplQg=; b=R6PfasfFL+Br1QcqVUoRQxzNS2Z0QfmQHHkUz1HzDMujfhRRj0HRnObVT1qNOb/d8q 1UTk1YJjUGIc6ClVGU2fEtYPmTIgumh05eoB5kHAxsTk4IpqU4tjuhd55S2lt7wh6kJi NQ1QeYcHyM/47By73/1NdqEEdNfaeL4GOnaADMGLDamecJvgVi6TvM/W3UwojpGXMeBW BP0ZVeiyUsDZlu7Q1fdd0+F4hL/cnjBNvL7NhEgow+5pAbHTqhuaVbKh0WvabdREuGoN Idy60l4+t2h/YUFix1RfHKgq1u0omyg4lmLfOMirmQE8NdUZMbaHTrRetQS/X4mz+Cqh 6nHw== X-Gm-Message-State: AOAM530xfr7tSYaUYdin9wLdAHnlr4q3lj+cioGLutfDYX5RQ5jfc7hb 4LFk7ZZpg12rkkBWDGVTOGKtKXqlmg== X-Google-Smtp-Source: ABdhPJw8Gldeq6H0br2wzbB7/Hq61EgLe84lN0RJB8PupfGJ53qUB5Sd72DFkV2IO1ScQLocofjUKZqheg== X-Received: from tabba.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:482]) (user=tabba job=sendgmr) by 2002:ad4:450b:: with SMTP id k11mr4520634qvu.0.1623764407702; Tue, 15 Jun 2021 06:40:07 -0700 (PDT) Date: Tue, 15 Jun 2021 14:39:44 +0100 In-Reply-To: <20210615133950.693489-1-tabba@google.com> Message-Id: <20210615133950.693489-8-tabba@google.com> Mime-Version: 1.0 References: <20210615133950.693489-1-tabba@google.com> X-Mailer: git-send-email 2.32.0.272.g935e593368-goog Subject: [PATCH v2 07/13] KVM: arm64: Add config register bit definitions From: Fuad Tabba To: kvmarm@lists.cs.columbia.edu Cc: maz@kernel.org, will@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, mark.rutland@arm.com, christoffer.dall@arm.com, pbonzini@redhat.com, drjones@redhat.com, qperret@google.com, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel-team@android.com, tabba@google.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210615_064011_691538_D29ECDFC X-CRM114-Status: GOOD ( 10.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add hardware configuration register bit definitions for HCR_EL2 and MDCR_EL2. Future patches toggle these hyp configuration register bits to trap on certain accesses. No functional change intended. Signed-off-by: Fuad Tabba --- arch/arm64/include/asm/kvm_arm.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index bee1ba6773fb..a78090071f1f 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -12,7 +12,11 @@ #include /* Hyp Configuration Register (HCR) bits */ +#define HCR_TID5 (UL(1) << 58) +#define HCR_DCT (UL(1) << 57) #define HCR_ATA (UL(1) << 56) +#define HCR_AMVOFFEN (UL(1) << 51) +#define HCR_FIEN (UL(1) << 47) #define HCR_FWB (UL(1) << 46) #define HCR_API (UL(1) << 41) #define HCR_APK (UL(1) << 40) @@ -55,6 +59,7 @@ #define HCR_PTW (UL(1) << 2) #define HCR_SWIO (UL(1) << 1) #define HCR_VM (UL(1) << 0) +#define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39)) /* * The bits we set in HCR: @@ -276,11 +281,21 @@ #define CPTR_EL2_TZ (1 << 8) #define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */ #define CPTR_EL2_DEFAULT CPTR_NVHE_EL2_RES1 +#define CPTR_NVHE_EL2_RES0 (GENMASK_ULL(63, 32) | \ + GENMASK_ULL(29, 21) | \ + GENMASK_ULL(19, 14) | \ + (UL(1) << 11)) /* Hyp Debug Configuration Register bits */ #define MDCR_EL2_E2TB_MASK (UL(0x3)) #define MDCR_EL2_E2TB_SHIFT (UL(24)) +#define MDCR_EL2_HPMFZS (UL(1) << 36) +#define MDCR_EL2_HPMFZO (UL(1) << 29) +#define MDCR_EL2_MTPME (UL(1) << 28) +#define MDCR_EL2_TDCC (UL(1) << 27) +#define MDCR_EL2_HCCD (UL(1) << 23) #define MDCR_EL2_TTRF (UL(1) << 19) +#define MDCR_EL2_HPMD (UL(1) << 17) #define MDCR_EL2_TPMS (UL(1) << 14) #define MDCR_EL2_E2PB_MASK (UL(0x3)) #define MDCR_EL2_E2PB_SHIFT (UL(12)) @@ -292,6 +307,12 @@ #define MDCR_EL2_TPM (UL(1) << 6) #define MDCR_EL2_TPMCR (UL(1) << 5) #define MDCR_EL2_HPMN_MASK (UL(0x1F)) +#define MDCR_EL2_RES0 (GENMASK_ULL(63, 37) | \ + GENMASK_ULL(35, 30) | \ + GENMASK_ULL(25, 24) | \ + GENMASK_ULL(22, 20) | \ + (UL(1) << 18) | \ + GENMASK_ULL(16, 15)) /* For compatibility with fault code shared with 32-bit */ #define FSC_FAULT ESR_ELx_FSC_FAULT -- 2.32.0.272.g935e593368-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel