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* [PATCH 00/11] Add imx8ulp basic dtsi support
@ 2021-06-07  8:39 Jacky Bai
  2021-06-07  8:39 ` [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
                   ` (10 more replies)
  0 siblings, 11 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

i.MX 8ULP is part of the ULP family with emphasis on extreme low-power
techniques using the 28 nm fully depleted silicon on insulator process.
Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric architecture,
however will add a third DSP domain for advanced voice/audio capability and
a Graphics domain where it is possible to access graphics resources from the
application side or the realtime side.

This patchset adds the basic dtsi support for i.MX8ULP, and also update the
dt-bindings docs for i.MX8ULP.

Jacky Bai (11):
  dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string
  dt-bindings: i2c: imx-lpi2c: Add imx8ulp compatible string
  dt-bindings: mmc: imx-esdhc: Add imx8ulp compatibe string
  dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string
  dt-bindings: spi: fsl-lpspi: Add imx8ulp compatible string
  dt-bindings: timer: tpm-timer: Add imx8ulp compatible string
  dt-bindings: watchdog: imx7ulp-wdt: Add imx8ulp compatible string
  dt-bindings: arm: fsl: Add binding for imx8ulp evk
  dt-bindings: clock: Add imx8ulp clock support
  arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp
  arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board

 .../devicetree/bindings/arm/fsl.yaml          |   6 +
 .../bindings/clock/imx8ulp-clock.yaml         |  72 ++
 .../devicetree/bindings/gpio/gpio-vf610.yaml  |   3 +
 .../bindings/i2c/i2c-imx-lpi2c.yaml           |   4 +-
 .../bindings/mmc/fsl-imx-esdhc.yaml           |   4 +
 .../bindings/serial/fsl-lpuart.yaml           |   4 +-
 .../bindings/spi/spi-fsl-lpspi.yaml           |  11 +-
 .../bindings/timer/nxp,tpm-timer.yaml         |   6 +-
 .../bindings/watchdog/fsl-imx7ulp-wdt.yaml    |   7 +-
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 143 +++
 .../boot/dts/freescale/imx8ulp-pinfunc.h      | 978 ++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8ulp.dtsi    | 474 +++++++++
 include/dt-bindings/clock/imx8ulp-clock.h     | 261 +++++
 14 files changed, 1965 insertions(+), 9 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
 create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
 create mode 100755 arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
 create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi
 create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h

-- 
2.26.2


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^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string
  2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
@ 2021-06-07  8:39 ` Jacky Bai
  2021-06-09 10:56   ` Linus Walleij
                     ` (2 more replies)
  2021-06-07  8:39 ` [PATCH 02/11] dt-bindings: i2c: imx-lpi2c: " Jacky Bai
                   ` (9 subsequent siblings)
  10 siblings, 3 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

Add the compatible string for i.MX8ULP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 Documentation/devicetree/bindings/gpio/gpio-vf610.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml
index 19738a457a58..e1359391d3a4 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml
+++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml
@@ -24,6 +24,9 @@ properties:
       - items:
           - const: fsl,imx7ulp-gpio
           - const: fsl,vf610-gpio
+      - items:
+          - const: fsl,imx8ulp-gpio
+          - const: fsl,imx7ulp-gpio
 
   reg:
     description: The first reg tuple represents the PORT module, the second tuple
-- 
2.26.2


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^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH 02/11] dt-bindings: i2c: imx-lpi2c: Add imx8ulp compatible string
  2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
  2021-06-07  8:39 ` [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
@ 2021-06-07  8:39 ` Jacky Bai
  2021-06-11 13:46   ` Dong Aisheng
  2021-06-16 23:43   ` Rob Herring
  2021-06-07  8:39 ` [PATCH 03/11] dt-bindings: mmc: imx-esdhc: Add imx8ulp compatibe string Jacky Bai
                   ` (8 subsequent siblings)
  10 siblings, 2 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

Add the compatible for i.MX8ULP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
index 29b9447f3b84..0875753c7d15 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
@@ -19,7 +19,9 @@ properties:
           - fsl,imx7ulp-lpi2c
           - fsl,imx8qm-lpi2c
       - items:
-          - const: fsl,imx8qxp-lpi2c
+          - enum:
+              - fsl,imx8qxp-lpi2c
+              - fsl,imx8ulp-lpi2c
           - const: fsl,imx7ulp-lpi2c
 
   reg:
-- 
2.26.2


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^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH 03/11] dt-bindings: mmc: imx-esdhc: Add imx8ulp compatibe string
  2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
  2021-06-07  8:39 ` [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
  2021-06-07  8:39 ` [PATCH 02/11] dt-bindings: i2c: imx-lpi2c: " Jacky Bai
@ 2021-06-07  8:39 ` Jacky Bai
  2021-06-11 13:50   ` Dong Aisheng
  2021-06-16 23:44   ` Rob Herring
  2021-06-07  8:39 ` [PATCH 04/11] dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string Jacky Bai
                   ` (7 subsequent siblings)
  10 siblings, 2 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

For i.MX8ULP, it uses two compatible strings, so update
the compatible string for i.MX8ULP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
index 369471814496..aeee2be1e36a 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
@@ -42,6 +42,10 @@ properties:
               - fsl,imx8qm-usdhc
               - fsl,imx8qxp-usdhc
           - const: fsl,imx7d-usdhc
+      - items:
+          - enum:
+              - fsl,imx8ulp-usdhc
+          - const: fsl,imx8mm-usdhc
 
   reg:
     maxItems: 1
-- 
2.26.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH 04/11] dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string
  2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
                   ` (2 preceding siblings ...)
  2021-06-07  8:39 ` [PATCH 03/11] dt-bindings: mmc: imx-esdhc: Add imx8ulp compatibe string Jacky Bai
@ 2021-06-07  8:39 ` Jacky Bai
  2021-06-11 13:52   ` Dong Aisheng
  2021-06-16 23:44   ` Rob Herring
  2021-06-07  8:39 ` [PATCH 05/11] dt-bindings: spi: fsl-lpspi: " Jacky Bai
                   ` (6 subsequent siblings)
  10 siblings, 2 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

For i.MX8ULP, it uses two compatible strings, so Update the
compatible string for i.MX8ULP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
index bd21060d26e0..5d3fde5d4d2b 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
@@ -22,7 +22,9 @@ properties:
           - fsl,imx7ulp-lpuart
           - fsl,imx8qm-lpuart
       - items:
-          - const: fsl,imx8qxp-lpuart
+          - enum:
+              - fsl,imx8qxp-lpuart
+              - fsl,imx8ulp-lpuart
           - const: fsl,imx7ulp-lpuart
 
   reg:
-- 
2.26.2


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH 05/11] dt-bindings: spi: fsl-lpspi: Add imx8ulp compatible string
  2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
                   ` (3 preceding siblings ...)
  2021-06-07  8:39 ` [PATCH 04/11] dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string Jacky Bai
@ 2021-06-07  8:39 ` Jacky Bai
  2021-06-11 13:57   ` Dong Aisheng
  2021-06-16 23:45   ` Rob Herring
  2021-06-07  8:39 ` [PATCH 06/11] dt-bindings: timer: tpm-timer: " Jacky Bai
                   ` (5 subsequent siblings)
  10 siblings, 2 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

For i.MX8ULP, it uses two compatible strings, so update the
comaptible strings.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 .../devicetree/bindings/spi/spi-fsl-lpspi.yaml        | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
index 312d8fee9dbb..1d46877fe46a 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
@@ -14,10 +14,13 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - fsl,imx7ulp-spi
-      - fsl,imx8qxp-spi
-
+    oneOf:
+      - enum:
+          - fsl,imx7ulp-spi
+          - fsl,imx8qxp-spi
+      - items:
+          - const: fsl,imx8ulp-spi
+          - const: fsl,imx7ulp-spi
   reg:
     maxItems: 1
 
-- 
2.26.2


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^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH 06/11] dt-bindings: timer: tpm-timer: Add imx8ulp compatible string
  2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
                   ` (4 preceding siblings ...)
  2021-06-07  8:39 ` [PATCH 05/11] dt-bindings: spi: fsl-lpspi: " Jacky Bai
@ 2021-06-07  8:39 ` Jacky Bai
  2021-06-11 13:58   ` Dong Aisheng
  2021-06-16 23:45   ` Rob Herring
  2021-06-07  8:39 ` [PATCH 07/11] dt-bindings: watchdog: imx7ulp-wdt: " Jacky Bai
                   ` (4 subsequent siblings)
  10 siblings, 2 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

For i.MX8ULP, it use two compatible strings, so update the
compatible strings for it.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
index edd9585f6726..f69773a8e4b9 100644
--- a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
@@ -19,7 +19,11 @@ description: |
 
 properties:
   compatible:
-    const: fsl,imx7ulp-tpm
+    oneOf:
+      - const: fsl,imx7ulp-tpm
+      - items:
+          - const: fsl,imx8ulp-tpm
+          - const: fsl,imx7ulp-tpm
 
   reg:
     maxItems: 1
-- 
2.26.2


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH 07/11] dt-bindings: watchdog: imx7ulp-wdt: Add imx8ulp compatible string
  2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
                   ` (5 preceding siblings ...)
  2021-06-07  8:39 ` [PATCH 06/11] dt-bindings: timer: tpm-timer: " Jacky Bai
@ 2021-06-07  8:39 ` Jacky Bai
  2021-06-11 13:58   ` Dong Aisheng
  2021-06-16 23:45   ` Rob Herring
  2021-06-07  8:39 ` [PATCH 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk Jacky Bai
                   ` (3 subsequent siblings)
  10 siblings, 2 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

For i.MX8ULP, it uses two compatible strings, so Add the compatible
string for i.MX8ULP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 .../devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml      | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
index 51d6d482bbc2..fb603a20e396 100644
--- a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
@@ -14,8 +14,11 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - fsl,imx7ulp-wdt
+    oneOf:
+      - const: fsl,imx7ulp-wdt
+      - items:
+          - const: fsl,imx8ulp-wdt
+          - const: fsl,imx7ulp-wdt
 
   reg:
     maxItems: 1
-- 
2.26.2


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^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk
  2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
                   ` (6 preceding siblings ...)
  2021-06-07  8:39 ` [PATCH 07/11] dt-bindings: watchdog: imx7ulp-wdt: " Jacky Bai
@ 2021-06-07  8:39 ` Jacky Bai
  2021-06-11 13:59   ` Dong Aisheng
  2021-06-16 23:46   ` Rob Herring
  2021-06-07  8:39 ` [PATCH 09/11] dt-bindings: clock: Add imx8ulp clock support Jacky Bai
                   ` (2 subsequent siblings)
  10 siblings, 2 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

Add the dt binding for i.MX8ULP EVK board.

i.MX 8ULP is part of the ULP family with emphasis on extreme
low-power techniques using the 28 nm fully depleted silicon on
insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
based on asymmetric architecture, however will add a third DSP
domain for advanced voice/audio capability and a Graphics domain
where it is possible to access graphics resources from the
application side or the realtime side.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index fce2a8670b49..e68a1b43b144 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -788,6 +788,12 @@ properties:
           - const: toradex,colibri-imx8x
           - const: fsl,imx8qxp
 
+      - description: i.MX8ULP based Boards
+        items:
+          - enum:
+              - fsl,imx8ulp-evk           # i.MX8ULP EVK Board
+          - const: fsl,imx8ulp
+
       - description:
           Freescale Vybrid Platform Device Tree Bindings
 
-- 
2.26.2


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^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH 09/11] dt-bindings: clock: Add imx8ulp clock support
  2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
                   ` (7 preceding siblings ...)
  2021-06-07  8:39 ` [PATCH 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk Jacky Bai
@ 2021-06-07  8:39 ` Jacky Bai
  2021-06-11 14:17   ` Dong Aisheng
  2021-06-16 23:47   ` Rob Herring
  2021-06-07  8:39 ` [PATCH 11/11] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board Jacky Bai
       [not found] ` <20210607083921.2668568-11-ping.bai@nxp.com>
  10 siblings, 2 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

Add the clock dt-binding file for i.MX8ULP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 .../bindings/clock/imx8ulp-clock.yaml         |  72 +++++
 include/dt-bindings/clock/imx8ulp-clock.h     | 261 ++++++++++++++++++
 2 files changed, 333 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
 create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h

diff --git a/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
new file mode 100644
index 000000000000..ffe7b713d4e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx8ulp-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8ULP Clock Control Module Binding
+
+maintainers:
+  - Jacky Bai <ping.bai@nxp.com>
+
+description: |
+  On i.MX8ULP, The clock sources generation, distribution and management is
+  under the control of several CGCs & PCCs modules. The CGC modules generate
+  and distribute clocks on the device. PCC modules control clock selection,
+  optional division and clock gating mode for peripherals
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8ulp-cgc1
+      - fsl,imx8ulp-cgc2
+      - fsl,imx8ulp-pcc3
+      - fsl,imx8ulp-pcc4
+      - fsl,imx8ulp-pcc5
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description:
+      specify the external clocks used by the CGC module, the clocks
+      are rosc, sosc, frosc, lposc
+    maxItems: 4
+
+  clock-names:
+    description:
+      specify the external clocks names used by the CGC module. the valid
+      clock names should rosc, sosc, frosc, lposc.
+    maxItems: 4
+
+  '#clock-cells':
+    const: 1
+    description:
+      The clock consumer should specify the desired clock by having the clock
+      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8ulp-clock.h
+      for the full list of i.MX8ULP clock IDs.
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  # Clock Control Module node:
+  - |
+    clock-controller@292c0000 {
+        compatible = "fsl,imx8ulp-cgc1";
+        reg = <0x292c0000 0x10000>;
+        clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
+        clock-names = "rosc", "sosc", "frosc", "lposc";
+        #clock-cells = <1>;
+    };
+
+  - |
+    clock-controller@292d0000 {
+        compatible = "fsl,imx8ulp-pcc3";
+        reg = <0x292d0000 0x10000>;
+        #clock-cells = <1>;
+    };
diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
new file mode 100644
index 000000000000..61518775f434
--- /dev/null
+++ b/include/dt-bindings/clock/imx8ulp-clock.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
+#define __DT_BINDINGS_CLOCK_IMX8ULP_H
+
+#define IMX8ULP_CLK_DUMMY			0
+#define IMX8ULP_CLK_ROSC			1
+#define IMX8ULP_CLK_FROSC			2
+#define IMX8ULP_CLK_LPOSC			3
+#define IMX8ULP_CLK_SOSC			4
+
+/* CGC1 */
+#define IMX8ULP_CLK_SPLL2			5
+#define IMX8ULP_CLK_SPLL3			6
+#define IMX8ULP_CLK_A35_SEL			7
+#define IMX8ULP_CLK_A35_DIV			8
+#define IMX8ULP_CLK_SPLL2_PRE_SEL		9
+#define IMX8ULP_CLK_SPLL3_PRE_SEL		10
+#define IMX8ULP_CLK_SPLL3_PFD0			11
+#define IMX8ULP_CLK_SPLL3_PFD1			12
+#define IMX8ULP_CLK_SPLL3_PFD2			13
+#define IMX8ULP_CLK_SPLL3_PFD3			14
+#define IMX8ULP_CLK_SPLL3_PFD0_DIV1		15
+#define IMX8ULP_CLK_SPLL3_PFD0_DIV2		16
+#define IMX8ULP_CLK_SPLL3_PFD1_DIV1		17
+#define IMX8ULP_CLK_SPLL3_PFD1_DIV2		18
+#define IMX8ULP_CLK_SPLL3_PFD2_DIV1		19
+#define IMX8ULP_CLK_SPLL3_PFD2_DIV2		20
+#define IMX8ULP_CLK_SPLL3_PFD3_DIV1		21
+#define IMX8ULP_CLK_SPLL3_PFD3_DIV2		22
+#define IMX8ULP_CLK_NIC_SEL			23
+#define IMX8ULP_CLK_NIC_AD_DIVPLAT		24
+#define IMX8ULP_CLK_NIC_PER_DIVPLAT		25
+#define IMX8ULP_CLK_XBAR_SEL			26
+#define IMX8ULP_CLK_XBAR_AD_DIVPLAT		27
+#define IMX8ULP_CLK_XBAR_DIVBUS			28
+#define IMX8ULP_CLK_XBAR_AD_SLOW		29
+#define IMX8ULP_CLK_SOSC_DIV1			30
+#define IMX8ULP_CLK_SOSC_DIV2			31
+#define IMX8ULP_CLK_SOSC_DIV3			32
+#define IMX8ULP_CLK_FROSC_DIV1			33
+#define IMX8ULP_CLK_FROSC_DIV2			34
+#define IMX8ULP_CLK_FROSC_DIV3			35
+#define IMX8ULP_CLK_SPLL3_VCODIV		36
+#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE	37
+#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE	38
+#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE	39
+#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE	40
+#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE	41
+#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE	42
+#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE	43
+#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE	44
+#define IMX8ULP_CLK_SOSC_DIV1_GATE		45
+#define IMX8ULP_CLK_SOSC_DIV2_GATE		46
+#define IMX8ULP_CLK_SOSC_DIV3_GATE		47
+#define IMX8ULP_CLK_FROSC_DIV1_GATE		48
+#define IMX8ULP_CLK_FROSC_DIV2_GATE		49
+#define IMX8ULP_CLK_FROSC_DIV3_GATE		50
+#define IMX8ULP_CLK_SAI4_SEL			51
+#define IMX8ULP_CLK_SAI5_SEL			52
+#define IMX8ULP_CLK_AUD_CLK1			53
+#define IMX8ULP_CLK_ARM				54
+#define IMX8ULP_CLK_ENET_TS_SEL			55
+
+#define IMX8ULP_CLK_CGC1_END			56
+
+/* CGC2 */
+#define IMX8ULP_CLK_PLL4_PRE_SEL	0
+#define IMX8ULP_CLK_PLL4		1
+#define IMX8ULP_CLK_PLL4_VCODIV		2
+#define IMX8ULP_CLK_DDR_SEL		3
+#define IMX8ULP_CLK_DDR_DIV		4
+#define IMX8ULP_CLK_LPAV_AXI_SEL	5
+#define IMX8ULP_CLK_LPAV_AXI_DIV	6
+#define IMX8ULP_CLK_LPAV_AHB_DIV	7
+#define IMX8ULP_CLK_LPAV_BUS_DIV	8
+#define IMX8ULP_CLK_PLL4_PFD0		9
+#define IMX8ULP_CLK_PLL4_PFD1		10
+#define IMX8ULP_CLK_PLL4_PFD2		11
+#define IMX8ULP_CLK_PLL4_PFD3		12
+#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE	13
+#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE	14
+#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE	15
+#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE	16
+#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE	17
+#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE	18
+#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE	19
+#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE	20
+#define IMX8ULP_CLK_PLL4_PFD0_DIV1	21
+#define IMX8ULP_CLK_PLL4_PFD0_DIV2	22
+#define IMX8ULP_CLK_PLL4_PFD1_DIV1	23
+#define IMX8ULP_CLK_PLL4_PFD1_DIV2	24
+#define IMX8ULP_CLK_PLL4_PFD2_DIV1	25
+#define IMX8ULP_CLK_PLL4_PFD2_DIV2	26
+#define IMX8ULP_CLK_PLL4_PFD3_DIV1	27
+#define IMX8ULP_CLK_PLL4_PFD3_DIV2	28
+#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE	29
+#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE	30
+#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE	31
+#define IMX8ULP_CLK_CGC2_SOSC_DIV1	32
+#define IMX8ULP_CLK_CGC2_SOSC_DIV2	33
+#define IMX8ULP_CLK_CGC2_SOSC_DIV3	34
+#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE	35
+#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE	36
+#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE	37
+#define IMX8ULP_CLK_CGC2_FROSC_DIV1	38
+#define IMX8ULP_CLK_CGC2_FROSC_DIV2	39
+#define IMX8ULP_CLK_CGC2_FROSC_DIV3	40
+#define IMX8ULP_CLK_AUD_CLK2		41
+#define IMX8ULP_CLK_SAI6_SEL		42
+#define IMX8ULP_CLK_SAI7_SEL		43
+#define IMX8ULP_CLK_SPDIF_SEL		44
+#define IMX8ULP_CLK_HIFI_SEL		45
+#define IMX8ULP_CLK_HIFI_DIVCORE	46
+#define IMX8ULP_CLK_HIFI_DIVPLAT	47
+#define IMX8ULP_CLK_DSI_PHY_REF		48
+
+#define IMX8ULP_CLK_CGC2_END		49
+
+/* PCC3 */
+#define IMX8ULP_CLK_WDOG3		0
+#define IMX8ULP_CLK_WDOG4		1
+#define IMX8ULP_CLK_LPIT1		2
+#define IMX8ULP_CLK_TPM4		3
+#define IMX8ULP_CLK_TPM5		4
+#define IMX8ULP_CLK_FLEXIO1		5
+#define IMX8ULP_CLK_I3C2		6
+#define IMX8ULP_CLK_LPI2C4		7
+#define IMX8ULP_CLK_LPI2C5		8
+#define IMX8ULP_CLK_LPUART4		9
+#define IMX8ULP_CLK_LPUART5		10
+#define IMX8ULP_CLK_LPSPI4		11
+#define IMX8ULP_CLK_LPSPI5		12
+#define IMX8ULP_CLK_DMA1_MP		13
+#define IMX8ULP_CLK_DMA1_CH0		14
+#define IMX8ULP_CLK_DMA1_CH1		15
+#define IMX8ULP_CLK_DMA1_CH2		16
+#define IMX8ULP_CLK_DMA1_CH3		17
+#define IMX8ULP_CLK_DMA1_CH4		18
+#define IMX8ULP_CLK_DMA1_CH5		19
+#define IMX8ULP_CLK_DMA1_CH6		20
+#define IMX8ULP_CLK_DMA1_CH7		21
+#define IMX8ULP_CLK_DMA1_CH8		22
+#define IMX8ULP_CLK_DMA1_CH9		23
+#define IMX8ULP_CLK_DMA1_CH10		24
+#define IMX8ULP_CLK_DMA1_CH11		25
+#define IMX8ULP_CLK_DMA1_CH12		26
+#define IMX8ULP_CLK_DMA1_CH13		27
+#define IMX8ULP_CLK_DMA1_CH14		28
+#define IMX8ULP_CLK_DMA1_CH15		29
+#define IMX8ULP_CLK_DMA1_CH16		30
+#define IMX8ULP_CLK_DMA1_CH17		31
+#define IMX8ULP_CLK_DMA1_CH18		32
+#define IMX8ULP_CLK_DMA1_CH19		33
+#define IMX8ULP_CLK_DMA1_CH20		34
+#define IMX8ULP_CLK_DMA1_CH21		35
+#define IMX8ULP_CLK_DMA1_CH22		36
+#define IMX8ULP_CLK_DMA1_CH23		37
+#define IMX8ULP_CLK_DMA1_CH24		38
+#define IMX8ULP_CLK_DMA1_CH25		39
+#define IMX8ULP_CLK_DMA1_CH26		40
+#define IMX8ULP_CLK_DMA1_CH27		41
+#define IMX8ULP_CLK_DMA1_CH28		42
+#define IMX8ULP_CLK_DMA1_CH29		43
+#define IMX8ULP_CLK_DMA1_CH30		44
+#define IMX8ULP_CLK_DMA1_CH31		45
+#define IMX8ULP_CLK_MU3_A		46
+
+#define IMX8ULP_CLK_PCC3_END		47
+
+/* PCC4 */
+#define IMX8ULP_CLK_FLEXSPI2		0
+#define IMX8ULP_CLK_TPM6		1
+#define IMX8ULP_CLK_TPM7		2
+#define IMX8ULP_CLK_LPI2C6		3
+#define IMX8ULP_CLK_LPI2C7		4
+#define IMX8ULP_CLK_LPUART6		5
+#define IMX8ULP_CLK_LPUART7		6
+#define IMX8ULP_CLK_SAI4		7
+#define IMX8ULP_CLK_SAI5		8
+#define IMX8ULP_CLK_PCTLE		9
+#define IMX8ULP_CLK_PCTLF		10
+#define IMX8ULP_CLK_USDHC0		11
+#define IMX8ULP_CLK_USDHC1		12
+#define IMX8ULP_CLK_USDHC2		13
+#define IMX8ULP_CLK_USB0		14
+#define IMX8ULP_CLK_USB0_PHY		15
+#define IMX8ULP_CLK_USB1		16
+#define IMX8ULP_CLK_USB1_PHY		17
+#define IMX8ULP_CLK_USB_XBAR		18
+#define IMX8ULP_CLK_ENET		19
+#define IMX8ULP_CLK_SFA1		20
+#define IMX8ULP_CLK_RGPIOE		21
+#define IMX8ULP_CLK_RGPIOF		22
+
+#define IMX8ULP_CLK_PCC4_END		23
+
+/* PCC5 */
+#define IMX8ULP_CLK_TPM8		0
+#define IMX8ULP_CLK_SAI6		1
+#define IMX8ULP_CLK_SAI7		2
+#define IMX8ULP_CLK_SPDIF		3
+#define IMX8ULP_CLK_ISI			4
+#define IMX8ULP_CLK_CSI_REGS 		5
+#define IMX8ULP_CLK_PCTLD		6
+#define IMX8ULP_CLK_CSI			7
+#define IMX8ULP_CLK_DSI			8
+#define IMX8ULP_CLK_WDOG5		9
+#define IMX8ULP_CLK_EPDC		10
+#define IMX8ULP_CLK_PXP			11
+#define IMX8ULP_CLK_SFA2		12
+#define IMX8ULP_CLK_GPU2D		13
+#define IMX8ULP_CLK_GPU3D		14
+#define IMX8ULP_CLK_DC_NANO		15
+#define IMX8ULP_CLK_CSI_CLK_UI 		16
+#define IMX8ULP_CLK_CSI_CLK_ESC		17
+#define IMX8ULP_CLK_RGPIOD		18
+#define IMX8ULP_CLK_DMA2_MP		19
+#define IMX8ULP_CLK_DMA2_CH0		20
+#define IMX8ULP_CLK_DMA2_CH1		21
+#define IMX8ULP_CLK_DMA2_CH2		22
+#define IMX8ULP_CLK_DMA2_CH3		23
+#define IMX8ULP_CLK_DMA2_CH4		24
+#define IMX8ULP_CLK_DMA2_CH5		25
+#define IMX8ULP_CLK_DMA2_CH6		26
+#define IMX8ULP_CLK_DMA2_CH7		27
+#define IMX8ULP_CLK_DMA2_CH8		28
+#define IMX8ULP_CLK_DMA2_CH9		29
+#define IMX8ULP_CLK_DMA2_CH10		30
+#define IMX8ULP_CLK_DMA2_CH11		31
+#define IMX8ULP_CLK_DMA2_CH12		32
+#define IMX8ULP_CLK_DMA2_CH13		33
+#define IMX8ULP_CLK_DMA2_CH14		34
+#define IMX8ULP_CLK_DMA2_CH15		35
+#define IMX8ULP_CLK_DMA2_CH16		36
+#define IMX8ULP_CLK_DMA2_CH17		37
+#define IMX8ULP_CLK_DMA2_CH18		38
+#define IMX8ULP_CLK_DMA2_CH19		39
+#define IMX8ULP_CLK_DMA2_CH20		40
+#define IMX8ULP_CLK_DMA2_CH21		41
+#define IMX8ULP_CLK_DMA2_CH22		42
+#define IMX8ULP_CLK_DMA2_CH23		43
+#define IMX8ULP_CLK_DMA2_CH24		44
+#define IMX8ULP_CLK_DMA2_CH25		45
+#define IMX8ULP_CLK_DMA2_CH26		46
+#define IMX8ULP_CLK_DMA2_CH27		47
+#define IMX8ULP_CLK_DMA2_CH28		48
+#define IMX8ULP_CLK_DMA2_CH29		49
+#define IMX8ULP_CLK_DMA2_CH30		50
+#define IMX8ULP_CLK_DMA2_CH31		51
+#define IMX8ULP_CLK_MU2_B		52
+#define IMX8ULP_CLK_MU3_B		53
+#define IMX8ULP_CLK_AVD_SIM		54
+#define IMX8ULP_CLK_DSI_TX_ESC		55
+
+#define IMX8ULP_CLK_PCC5_END		56
+
+#endif
-- 
2.26.2


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^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH 11/11] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board
  2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
                   ` (8 preceding siblings ...)
  2021-06-07  8:39 ` [PATCH 09/11] dt-bindings: clock: Add imx8ulp clock support Jacky Bai
@ 2021-06-07  8:39 ` Jacky Bai
  2021-06-11 14:43   ` Dong Aisheng
       [not found] ` <20210607083921.2668568-11-ping.bai@nxp.com>
  10 siblings, 1 reply; 36+ messages in thread
From: Jacky Bai @ 2021-06-07  8:39 UTC (permalink / raw)
  To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
  Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel

Add the basic dts file for i.MX8ULP EVK board.
Only the necessary devices for minimal system boot up are enabled:
enet, emmc, usb, console uart.

some of the devices' pin status may lost during low power mode,
so additional sleep pinctrl properties are included by default.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 143 ++++++++++++++++++
 2 files changed, 144 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 25806c4924cb..8c24a05d55af 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -65,5 +65,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
 
 dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
new file mode 100644
index 000000000000..f4db04f357fe
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8ulp.dtsi"
+
+/ {
+	model = "NXP i.MX8ULP EVK";
+	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
+
+	chosen {
+		stdout-path = &lpuart5;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy: ethernet-phy {
+			reg = <1>;
+			micrel,led-mode = <1>;
+		};
+	};
+};
+
+&lpuart5 {
+	/* console */
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_lpuart5>;
+	pinctrl-1 = <&pinctrl_lpuart5>;
+	status = "okay";
+};
+
+&usbotg1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_otgid1>;
+	pinctrl-1 = <&pinctrl_otgid1>;
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbphy1 {
+	status = "okay";
+};
+
+&usbmisc1 {
+	status = "okay";
+};
+
+&usbotg2 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_otgid2>;
+	pinctrl-1 = <&pinctrl_otgid2>;
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbphy2 {
+	status = "okay";
+};
+
+&usbmisc2 {
+	status = "okay";
+};
+
+&usdhc0 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc0>;
+	pinctrl-1 = <&pinctrl_usdhc0>;
+	non-removable;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX8ULP_PAD_PTE15__ENET0_MDC     0x43
+			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
+			MX8ULP_PAD_PTE17__ENET0_RXER    0x43
+			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
+			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
+			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
+			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
+			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
+			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
+			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
+			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
+		>;
+	};
+
+	pinctrl_lpuart5: lpuart5grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
+			MX8ULP_PAD_PTF15__LPUART5_RX	0x3
+		>;
+	};
+
+	pinctrl_otgid1: usb1grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTF2__USB0_ID	0x10003
+		>;
+	};
+
+	pinctrl_otgid2: usb2grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTD23__USB1_ID	0x10003
+		>;
+	};
+
+	pinctrl_usdhc0: usdhc0grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
+			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
+			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
+			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
+			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
+			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
+			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
+			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
+			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
+			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
+			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
+		>;
+	};
+};
-- 
2.26.2


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^ permalink raw reply related	[flat|nested] 36+ messages in thread

* Re: [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
@ 2021-06-09 10:56   ` Linus Walleij
  2021-06-11 13:45   ` Dong Aisheng
  2021-06-16 23:42   ` Rob Herring
  2 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2021-06-09 10:56 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer, Dong Aisheng,
	Fabio Estevam, Sascha Hauer, NXP Linux Team,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux ARM

On Mon, Jun 7, 2021 at 10:29 AM Jacky Bai <ping.bai@nxp.com> wrote:

> Add the compatible string for i.MX8ULP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
  2021-06-09 10:56   ` Linus Walleij
@ 2021-06-11 13:45   ` Dong Aisheng
  2021-06-16 23:42   ` Rob Herring
  2 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-06-11 13:45 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer,
	Linus Walleij, Dong Aisheng, Fabio Estevam, Sascha Hauer,
	dl-linux-imx, devicetree,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Mon, Jun 7, 2021 at 4:31 PM Jacky Bai <ping.bai@nxp.com> wrote:
>
> Add the compatible string for i.MX8ULP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  Documentation/devicetree/bindings/gpio/gpio-vf610.yaml | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml
> index 19738a457a58..e1359391d3a4 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml
> +++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml
> @@ -24,6 +24,9 @@ properties:
>        - items:
>            - const: fsl,imx7ulp-gpio
>            - const: fsl,vf610-gpio
> +      - items:
> +          - const: fsl,imx8ulp-gpio
> +          - const: fsl,imx7ulp-gpio
>
>    reg:
>      description: The first reg tuple represents the PORT module, the second tuple
> --
> 2.26.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 02/11] dt-bindings: i2c: imx-lpi2c: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 02/11] dt-bindings: i2c: imx-lpi2c: " Jacky Bai
@ 2021-06-11 13:46   ` Dong Aisheng
  2021-06-16 23:43   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-06-11 13:46 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer,
	Linus Walleij, Dong Aisheng, Fabio Estevam, Sascha Hauer,
	dl-linux-imx, devicetree,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Mon, Jun 7, 2021 at 4:31 PM Jacky Bai <ping.bai@nxp.com> wrote:
>
> Add the compatible for i.MX8ULP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
> index 29b9447f3b84..0875753c7d15 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
> +++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
> @@ -19,7 +19,9 @@ properties:
>            - fsl,imx7ulp-lpi2c
>            - fsl,imx8qm-lpi2c
>        - items:
> -          - const: fsl,imx8qxp-lpi2c
> +          - enum:
> +              - fsl,imx8qxp-lpi2c
> +              - fsl,imx8ulp-lpi2c
>            - const: fsl,imx7ulp-lpi2c
>
>    reg:
> --
> 2.26.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 03/11] dt-bindings: mmc: imx-esdhc: Add imx8ulp compatibe string
  2021-06-07  8:39 ` [PATCH 03/11] dt-bindings: mmc: imx-esdhc: Add imx8ulp compatibe string Jacky Bai
@ 2021-06-11 13:50   ` Dong Aisheng
  2021-06-16 23:44   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-06-11 13:50 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer,
	Linus Walleij, Dong Aisheng, Fabio Estevam, Sascha Hauer,
	dl-linux-imx, devicetree,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Mon, Jun 7, 2021 at 4:32 PM Jacky Bai <ping.bai@nxp.com> wrote:
>
> For i.MX8ULP, it uses two compatible strings, so update
> the compatible string for i.MX8ULP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Probably the commit message is better to be improved.
e.g.
uSDHC on i.MX8ULP is derived from i.MX8MM.

Otherwise
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
> index 369471814496..aeee2be1e36a 100644
> --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
> @@ -42,6 +42,10 @@ properties:
>                - fsl,imx8qm-usdhc
>                - fsl,imx8qxp-usdhc
>            - const: fsl,imx7d-usdhc
> +      - items:
> +          - enum:
> +              - fsl,imx8ulp-usdhc
> +          - const: fsl,imx8mm-usdhc
>
>    reg:
>      maxItems: 1
> --
> 2.26.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 04/11] dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 04/11] dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string Jacky Bai
@ 2021-06-11 13:52   ` Dong Aisheng
  2021-06-16 23:44   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-06-11 13:52 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer,
	Linus Walleij, Dong Aisheng, Fabio Estevam, Sascha Hauer,
	dl-linux-imx, devicetree,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

n Mon, Jun 7, 2021 at 4:33 PM Jacky Bai <ping.bai@nxp.com> wrote:
>
> For i.MX8ULP, it uses two compatible strings, so Update the
> compatible string for i.MX8ULP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>


As the previous patch, the commit message is better to be improved.
Otherwise
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
> index bd21060d26e0..5d3fde5d4d2b 100644
> --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
> +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
> @@ -22,7 +22,9 @@ properties:
>            - fsl,imx7ulp-lpuart
>            - fsl,imx8qm-lpuart
>        - items:
> -          - const: fsl,imx8qxp-lpuart
> +          - enum:
> +              - fsl,imx8qxp-lpuart
> +              - fsl,imx8ulp-lpuart
>            - const: fsl,imx7ulp-lpuart
>
>    reg:
> --
> 2.26.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 05/11] dt-bindings: spi: fsl-lpspi: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 05/11] dt-bindings: spi: fsl-lpspi: " Jacky Bai
@ 2021-06-11 13:57   ` Dong Aisheng
  2021-06-16 23:45   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-06-11 13:57 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer,
	Linus Walleij, Dong Aisheng, Fabio Estevam, Sascha Hauer,
	dl-linux-imx, devicetree,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Mon, Jun 7, 2021 at 4:33 PM Jacky Bai <ping.bai@nxp.com> wrote:
>
> For i.MX8ULP, it uses two compatible strings, so update the
> comaptible strings.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

As previously mentioned, pls improve commit message,
otherwise:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  .../devicetree/bindings/spi/spi-fsl-lpspi.yaml        | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
> index 312d8fee9dbb..1d46877fe46a 100644
> --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
> @@ -14,10 +14,13 @@ allOf:
>
>  properties:
>    compatible:
> -    enum:
> -      - fsl,imx7ulp-spi
> -      - fsl,imx8qxp-spi
> -
> +    oneOf:
> +      - enum:
> +          - fsl,imx7ulp-spi
> +          - fsl,imx8qxp-spi
> +      - items:
> +          - const: fsl,imx8ulp-spi
> +          - const: fsl,imx7ulp-spi
>    reg:
>      maxItems: 1
>
> --
> 2.26.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 06/11] dt-bindings: timer: tpm-timer: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 06/11] dt-bindings: timer: tpm-timer: " Jacky Bai
@ 2021-06-11 13:58   ` Dong Aisheng
  2021-06-16 23:45   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-06-11 13:58 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer,
	Linus Walleij, Dong Aisheng, Fabio Estevam, Sascha Hauer,
	dl-linux-imx, devicetree,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Mon, Jun 7, 2021 at 4:34 PM Jacky Bai <ping.bai@nxp.com> wrote:
>
> For i.MX8ULP, it use two compatible strings, so update the
> compatible strings for it.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

As previously mentioned, pls improve commit message,
otherwise:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
> index edd9585f6726..f69773a8e4b9 100644
> --- a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
> +++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
> @@ -19,7 +19,11 @@ description: |
>
>  properties:
>    compatible:
> -    const: fsl,imx7ulp-tpm
> +    oneOf:
> +      - const: fsl,imx7ulp-tpm
> +      - items:
> +          - const: fsl,imx8ulp-tpm
> +          - const: fsl,imx7ulp-tpm
>
>    reg:
>      maxItems: 1
> --
> 2.26.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 07/11] dt-bindings: watchdog: imx7ulp-wdt: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 07/11] dt-bindings: watchdog: imx7ulp-wdt: " Jacky Bai
@ 2021-06-11 13:58   ` Dong Aisheng
  2021-06-16 23:45   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-06-11 13:58 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer,
	Linus Walleij, Dong Aisheng, Fabio Estevam, Sascha Hauer,
	dl-linux-imx, devicetree,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Mon, Jun 7, 2021 at 4:35 PM Jacky Bai <ping.bai@nxp.com> wrote:
>
> For i.MX8ULP, it uses two compatible strings, so Add the compatible
> string for i.MX8ULP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

As previously mentioned, pls improve commit message,
otherwise:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  .../devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml      | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
> index 51d6d482bbc2..fb603a20e396 100644
> --- a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
> @@ -14,8 +14,11 @@ allOf:
>
>  properties:
>    compatible:
> -    enum:
> -      - fsl,imx7ulp-wdt
> +    oneOf:
> +      - const: fsl,imx7ulp-wdt
> +      - items:
> +          - const: fsl,imx8ulp-wdt
> +          - const: fsl,imx7ulp-wdt
>
>    reg:
>      maxItems: 1
> --
> 2.26.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk
  2021-06-07  8:39 ` [PATCH 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk Jacky Bai
@ 2021-06-11 13:59   ` Dong Aisheng
  2021-06-16 23:46   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-06-11 13:59 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer,
	Linus Walleij, Dong Aisheng, Fabio Estevam, Sascha Hauer,
	dl-linux-imx, devicetree,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Mon, Jun 7, 2021 at 4:36 PM Jacky Bai <ping.bai@nxp.com> wrote:
>
> Add the dt binding for i.MX8ULP EVK board.
>
> i.MX 8ULP is part of the ULP family with emphasis on extreme
> low-power techniques using the 28 nm fully depleted silicon on
> insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
> based on asymmetric architecture, however will add a third DSP
> domain for advanced voice/audio capability and a Graphics domain
> where it is possible to access graphics resources from the
> application side or the realtime side.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index fce2a8670b49..e68a1b43b144 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -788,6 +788,12 @@ properties:
>            - const: toradex,colibri-imx8x
>            - const: fsl,imx8qxp
>
> +      - description: i.MX8ULP based Boards
> +        items:
> +          - enum:
> +              - fsl,imx8ulp-evk           # i.MX8ULP EVK Board
> +          - const: fsl,imx8ulp
> +
>        - description:
>            Freescale Vybrid Platform Device Tree Bindings
>
> --
> 2.26.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 09/11] dt-bindings: clock: Add imx8ulp clock support
  2021-06-07  8:39 ` [PATCH 09/11] dt-bindings: clock: Add imx8ulp clock support Jacky Bai
@ 2021-06-11 14:17   ` Dong Aisheng
  2021-06-16 23:47   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-06-11 14:17 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer,
	Linus Walleij, Dong Aisheng, Fabio Estevam, Sascha Hauer,
	dl-linux-imx, devicetree,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Mon, Jun 7, 2021 at 4:39 PM Jacky Bai <ping.bai@nxp.com> wrote:
>
> Add the clock dt-binding file for i.MX8ULP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  .../bindings/clock/imx8ulp-clock.yaml         |  72 +++++
>  include/dt-bindings/clock/imx8ulp-clock.h     | 261 ++++++++++++++++++
>  2 files changed, 333 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
>  create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h
>
> diff --git a/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> new file mode 100644
> index 000000000000..ffe7b713d4e7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/imx8ulp-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8ULP Clock Control Module Binding
> +
> +maintainers:
> +  - Jacky Bai <ping.bai@nxp.com>
> +
> +description: |
> +  On i.MX8ULP, The clock sources generation, distribution and management is
> +  under the control of several CGCs & PCCs modules. The CGC modules generate
> +  and distribute clocks on the device. PCC modules control clock selection,
> +  optional division and clock gating mode for peripherals
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx8ulp-cgc1
> +      - fsl,imx8ulp-cgc2
> +      - fsl,imx8ulp-pcc3
> +      - fsl,imx8ulp-pcc4
> +      - fsl,imx8ulp-pcc5
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    description:
> +      specify the external clocks used by the CGC module, the clocks
> +      are rosc, sosc, frosc, lposc
> +    maxItems: 4
> +
> +  clock-names:
> +    description:
> +      specify the external clocks names used by the CGC module. the valid
> +      clock names should rosc, sosc, frosc, lposc.

pls list const names for schema to check,
then you don't need to have description property

> +    maxItems: 4
> +
> +  '#clock-cells':
> +    const: 1
> +    description:
> +      The clock consumer should specify the desired clock by having the clock
> +      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8ulp-clock.h
> +      for the full list of i.MX8ULP clock IDs.
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#clock-cells'
> +

missing clocks/clock-names?

> +additionalProperties: false
> +
> +examples:
> +  # Clock Control Module node:
> +  - |
> +    clock-controller@292c0000 {
> +        compatible = "fsl,imx8ulp-cgc1";
> +        reg = <0x292c0000 0x10000>;
> +        clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
> +        clock-names = "rosc", "sosc", "frosc", "lposc";
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    clock-controller@292d0000 {
> +        compatible = "fsl,imx8ulp-pcc3";
> +        reg = <0x292d0000 0x10000>;
> +        #clock-cells = <1>;
> +    };
> diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
> new file mode 100644
> index 000000000000..61518775f434
> --- /dev/null
> +++ b/include/dt-bindings/clock/imx8ulp-clock.h
> @@ -0,0 +1,261 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
> +#define __DT_BINDINGS_CLOCK_IMX8ULP_H
> +
> +#define IMX8ULP_CLK_DUMMY                      0
> +#define IMX8ULP_CLK_ROSC                       1
> +#define IMX8ULP_CLK_FROSC                      2
> +#define IMX8ULP_CLK_LPOSC                      3
> +#define IMX8ULP_CLK_SOSC                       4
> +
> +/* CGC1 */

Should this be on the top to avoid confusing?

Regards
Aisheng

> +#define IMX8ULP_CLK_SPLL2                      5
> +#define IMX8ULP_CLK_SPLL3                      6
> +#define IMX8ULP_CLK_A35_SEL                    7
> +#define IMX8ULP_CLK_A35_DIV                    8
> +#define IMX8ULP_CLK_SPLL2_PRE_SEL              9
> +#define IMX8ULP_CLK_SPLL3_PRE_SEL              10
> +#define IMX8ULP_CLK_SPLL3_PFD0                 11
> +#define IMX8ULP_CLK_SPLL3_PFD1                 12
> +#define IMX8ULP_CLK_SPLL3_PFD2                 13
> +#define IMX8ULP_CLK_SPLL3_PFD3                 14
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1            15
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2            16
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1            17
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2            18
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1            19
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2            20
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1            21
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2            22
> +#define IMX8ULP_CLK_NIC_SEL                    23
> +#define IMX8ULP_CLK_NIC_AD_DIVPLAT             24
> +#define IMX8ULP_CLK_NIC_PER_DIVPLAT            25
> +#define IMX8ULP_CLK_XBAR_SEL                   26
> +#define IMX8ULP_CLK_XBAR_AD_DIVPLAT            27
> +#define IMX8ULP_CLK_XBAR_DIVBUS                        28
> +#define IMX8ULP_CLK_XBAR_AD_SLOW               29
> +#define IMX8ULP_CLK_SOSC_DIV1                  30
> +#define IMX8ULP_CLK_SOSC_DIV2                  31
> +#define IMX8ULP_CLK_SOSC_DIV3                  32
> +#define IMX8ULP_CLK_FROSC_DIV1                 33
> +#define IMX8ULP_CLK_FROSC_DIV2                 34
> +#define IMX8ULP_CLK_FROSC_DIV3                 35
> +#define IMX8ULP_CLK_SPLL3_VCODIV               36
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE       37
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE       38
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE       39
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE       40
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE       41
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE       42
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE       43
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE       44
> +#define IMX8ULP_CLK_SOSC_DIV1_GATE             45
> +#define IMX8ULP_CLK_SOSC_DIV2_GATE             46
> +#define IMX8ULP_CLK_SOSC_DIV3_GATE             47
> +#define IMX8ULP_CLK_FROSC_DIV1_GATE            48
> +#define IMX8ULP_CLK_FROSC_DIV2_GATE            49
> +#define IMX8ULP_CLK_FROSC_DIV3_GATE            50
> +#define IMX8ULP_CLK_SAI4_SEL                   51
> +#define IMX8ULP_CLK_SAI5_SEL                   52
> +#define IMX8ULP_CLK_AUD_CLK1                   53
> +#define IMX8ULP_CLK_ARM                                54
> +#define IMX8ULP_CLK_ENET_TS_SEL                        55
> +
> +#define IMX8ULP_CLK_CGC1_END                   56
> +
> +/* CGC2 */
> +#define IMX8ULP_CLK_PLL4_PRE_SEL       0
> +#define IMX8ULP_CLK_PLL4               1
> +#define IMX8ULP_CLK_PLL4_VCODIV                2
> +#define IMX8ULP_CLK_DDR_SEL            3
> +#define IMX8ULP_CLK_DDR_DIV            4
> +#define IMX8ULP_CLK_LPAV_AXI_SEL       5
> +#define IMX8ULP_CLK_LPAV_AXI_DIV       6
> +#define IMX8ULP_CLK_LPAV_AHB_DIV       7
> +#define IMX8ULP_CLK_LPAV_BUS_DIV       8
> +#define IMX8ULP_CLK_PLL4_PFD0          9
> +#define IMX8ULP_CLK_PLL4_PFD1          10
> +#define IMX8ULP_CLK_PLL4_PFD2          11
> +#define IMX8ULP_CLK_PLL4_PFD3          12
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE        13
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE        14
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE        15
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE        16
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE        17
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE        18
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE        19
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE        20
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV1     21
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV2     22
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV1     23
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV2     24
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV1     25
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV2     26
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV1     27
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV2     28
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE        29
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE        30
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE        31
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV1     32
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV2     33
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV3     34
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE       35
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE       36
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE       37
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV1    38
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV2    39
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV3    40
> +#define IMX8ULP_CLK_AUD_CLK2           41
> +#define IMX8ULP_CLK_SAI6_SEL           42
> +#define IMX8ULP_CLK_SAI7_SEL           43
> +#define IMX8ULP_CLK_SPDIF_SEL          44
> +#define IMX8ULP_CLK_HIFI_SEL           45
> +#define IMX8ULP_CLK_HIFI_DIVCORE       46
> +#define IMX8ULP_CLK_HIFI_DIVPLAT       47
> +#define IMX8ULP_CLK_DSI_PHY_REF                48
> +
> +#define IMX8ULP_CLK_CGC2_END           49
> +
> +/* PCC3 */
> +#define IMX8ULP_CLK_WDOG3              0
> +#define IMX8ULP_CLK_WDOG4              1
> +#define IMX8ULP_CLK_LPIT1              2
> +#define IMX8ULP_CLK_TPM4               3
> +#define IMX8ULP_CLK_TPM5               4
> +#define IMX8ULP_CLK_FLEXIO1            5
> +#define IMX8ULP_CLK_I3C2               6
> +#define IMX8ULP_CLK_LPI2C4             7
> +#define IMX8ULP_CLK_LPI2C5             8
> +#define IMX8ULP_CLK_LPUART4            9
> +#define IMX8ULP_CLK_LPUART5            10
> +#define IMX8ULP_CLK_LPSPI4             11
> +#define IMX8ULP_CLK_LPSPI5             12
> +#define IMX8ULP_CLK_DMA1_MP            13
> +#define IMX8ULP_CLK_DMA1_CH0           14
> +#define IMX8ULP_CLK_DMA1_CH1           15
> +#define IMX8ULP_CLK_DMA1_CH2           16
> +#define IMX8ULP_CLK_DMA1_CH3           17
> +#define IMX8ULP_CLK_DMA1_CH4           18
> +#define IMX8ULP_CLK_DMA1_CH5           19
> +#define IMX8ULP_CLK_DMA1_CH6           20
> +#define IMX8ULP_CLK_DMA1_CH7           21
> +#define IMX8ULP_CLK_DMA1_CH8           22
> +#define IMX8ULP_CLK_DMA1_CH9           23
> +#define IMX8ULP_CLK_DMA1_CH10          24
> +#define IMX8ULP_CLK_DMA1_CH11          25
> +#define IMX8ULP_CLK_DMA1_CH12          26
> +#define IMX8ULP_CLK_DMA1_CH13          27
> +#define IMX8ULP_CLK_DMA1_CH14          28
> +#define IMX8ULP_CLK_DMA1_CH15          29
> +#define IMX8ULP_CLK_DMA1_CH16          30
> +#define IMX8ULP_CLK_DMA1_CH17          31
> +#define IMX8ULP_CLK_DMA1_CH18          32
> +#define IMX8ULP_CLK_DMA1_CH19          33
> +#define IMX8ULP_CLK_DMA1_CH20          34
> +#define IMX8ULP_CLK_DMA1_CH21          35
> +#define IMX8ULP_CLK_DMA1_CH22          36
> +#define IMX8ULP_CLK_DMA1_CH23          37
> +#define IMX8ULP_CLK_DMA1_CH24          38
> +#define IMX8ULP_CLK_DMA1_CH25          39
> +#define IMX8ULP_CLK_DMA1_CH26          40
> +#define IMX8ULP_CLK_DMA1_CH27          41
> +#define IMX8ULP_CLK_DMA1_CH28          42
> +#define IMX8ULP_CLK_DMA1_CH29          43
> +#define IMX8ULP_CLK_DMA1_CH30          44
> +#define IMX8ULP_CLK_DMA1_CH31          45
> +#define IMX8ULP_CLK_MU3_A              46
> +
> +#define IMX8ULP_CLK_PCC3_END           47
> +
> +/* PCC4 */
> +#define IMX8ULP_CLK_FLEXSPI2           0
> +#define IMX8ULP_CLK_TPM6               1
> +#define IMX8ULP_CLK_TPM7               2
> +#define IMX8ULP_CLK_LPI2C6             3
> +#define IMX8ULP_CLK_LPI2C7             4
> +#define IMX8ULP_CLK_LPUART6            5
> +#define IMX8ULP_CLK_LPUART7            6
> +#define IMX8ULP_CLK_SAI4               7
> +#define IMX8ULP_CLK_SAI5               8
> +#define IMX8ULP_CLK_PCTLE              9
> +#define IMX8ULP_CLK_PCTLF              10
> +#define IMX8ULP_CLK_USDHC0             11
> +#define IMX8ULP_CLK_USDHC1             12
> +#define IMX8ULP_CLK_USDHC2             13
> +#define IMX8ULP_CLK_USB0               14
> +#define IMX8ULP_CLK_USB0_PHY           15
> +#define IMX8ULP_CLK_USB1               16
> +#define IMX8ULP_CLK_USB1_PHY           17
> +#define IMX8ULP_CLK_USB_XBAR           18
> +#define IMX8ULP_CLK_ENET               19
> +#define IMX8ULP_CLK_SFA1               20
> +#define IMX8ULP_CLK_RGPIOE             21
> +#define IMX8ULP_CLK_RGPIOF             22
> +
> +#define IMX8ULP_CLK_PCC4_END           23
> +
> +/* PCC5 */
> +#define IMX8ULP_CLK_TPM8               0
> +#define IMX8ULP_CLK_SAI6               1
> +#define IMX8ULP_CLK_SAI7               2
> +#define IMX8ULP_CLK_SPDIF              3
> +#define IMX8ULP_CLK_ISI                        4
> +#define IMX8ULP_CLK_CSI_REGS           5
> +#define IMX8ULP_CLK_PCTLD              6
> +#define IMX8ULP_CLK_CSI                        7
> +#define IMX8ULP_CLK_DSI                        8
> +#define IMX8ULP_CLK_WDOG5              9
> +#define IMX8ULP_CLK_EPDC               10
> +#define IMX8ULP_CLK_PXP                        11
> +#define IMX8ULP_CLK_SFA2               12
> +#define IMX8ULP_CLK_GPU2D              13
> +#define IMX8ULP_CLK_GPU3D              14
> +#define IMX8ULP_CLK_DC_NANO            15
> +#define IMX8ULP_CLK_CSI_CLK_UI                 16
> +#define IMX8ULP_CLK_CSI_CLK_ESC                17
> +#define IMX8ULP_CLK_RGPIOD             18
> +#define IMX8ULP_CLK_DMA2_MP            19
> +#define IMX8ULP_CLK_DMA2_CH0           20
> +#define IMX8ULP_CLK_DMA2_CH1           21
> +#define IMX8ULP_CLK_DMA2_CH2           22
> +#define IMX8ULP_CLK_DMA2_CH3           23
> +#define IMX8ULP_CLK_DMA2_CH4           24
> +#define IMX8ULP_CLK_DMA2_CH5           25
> +#define IMX8ULP_CLK_DMA2_CH6           26
> +#define IMX8ULP_CLK_DMA2_CH7           27
> +#define IMX8ULP_CLK_DMA2_CH8           28
> +#define IMX8ULP_CLK_DMA2_CH9           29
> +#define IMX8ULP_CLK_DMA2_CH10          30
> +#define IMX8ULP_CLK_DMA2_CH11          31
> +#define IMX8ULP_CLK_DMA2_CH12          32
> +#define IMX8ULP_CLK_DMA2_CH13          33
> +#define IMX8ULP_CLK_DMA2_CH14          34
> +#define IMX8ULP_CLK_DMA2_CH15          35
> +#define IMX8ULP_CLK_DMA2_CH16          36
> +#define IMX8ULP_CLK_DMA2_CH17          37
> +#define IMX8ULP_CLK_DMA2_CH18          38
> +#define IMX8ULP_CLK_DMA2_CH19          39
> +#define IMX8ULP_CLK_DMA2_CH20          40
> +#define IMX8ULP_CLK_DMA2_CH21          41
> +#define IMX8ULP_CLK_DMA2_CH22          42
> +#define IMX8ULP_CLK_DMA2_CH23          43
> +#define IMX8ULP_CLK_DMA2_CH24          44
> +#define IMX8ULP_CLK_DMA2_CH25          45
> +#define IMX8ULP_CLK_DMA2_CH26          46
> +#define IMX8ULP_CLK_DMA2_CH27          47
> +#define IMX8ULP_CLK_DMA2_CH28          48
> +#define IMX8ULP_CLK_DMA2_CH29          49
> +#define IMX8ULP_CLK_DMA2_CH30          50
> +#define IMX8ULP_CLK_DMA2_CH31          51
> +#define IMX8ULP_CLK_MU2_B              52
> +#define IMX8ULP_CLK_MU3_B              53
> +#define IMX8ULP_CLK_AVD_SIM            54
> +#define IMX8ULP_CLK_DSI_TX_ESC         55
> +
> +#define IMX8ULP_CLK_PCC5_END           56
> +
> +#endif
> --
> 2.26.2
>
>
> _______________________________________________
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> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* RE: [PATCH 10/11] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp
       [not found] ` <20210607083921.2668568-11-ping.bai@nxp.com>
@ 2021-06-11 14:40   ` Aisheng Dong
  2021-06-16 23:51   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Aisheng Dong @ 2021-06-11 14:40 UTC (permalink / raw)
  To: Jacky Bai, robh+dt, shawnguo, sboyd, s.hauer, linus.walleij
  Cc: festevam, kernel, dl-linux-imx, devicetree, linux-arm-kernel

> From: Jacky Bai <ping.bai@nxp.com>
> Sent: Monday, June 7, 2021 4:39 PM
> 
> i.MX 8ULP is part of the ULP family with emphasis on extreme
> low-power techniques using the 28 nm fully depleted silicon on
> insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
> based on asymmetric architecture, however will add a third DSP
> domain for advanced voice/audio capability and a Graphics domain
> where it is possible to access graphics resources from the
> application side or the realtime side.
> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

The patch mostly looks good to me.
Only a few minor comments.

> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> new file mode 100644
> index 000000000000..469c2dcd4636
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> @@ -0,0 +1,474 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +#include <dt-bindings/clock/imx8ulp-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "imx8ulp-pinfunc.h"
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		ethernet0 = &fec;
> +		gpio0 = &gpiod;
> +		gpio1 = &gpioe;
> +		gpio2 = &gpiof;
> +		mmc0 = &usdhc0;
> +		mmc1 = &usdhc1;
> +		mmc2 = &usdhc2;
> +		serial0 = &lpuart4;
> +		serial1 = &lpuart5;
> +		serial2 = &lpuart6;
> +		serial3 = &lpuart7;
> +		usbphy0 = &usbphy1;
> +		usbphy1 = &usbphy2;
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		A35_0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&A35_L2>;
> +		};
> +
> +		A35_1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x0 0x1>;
> +			enable-method = "psci";
> +			next-level-cache = <&A35_L2>;
> +		};
> +
> +		A35_L2: l2-cache0 {
> +			compatible = "cache";
> +		};
> +	};
> +
> +	gic: interrupt-controller@2d400000 {
> +		compatible = "arm,gic-v3";
> +		reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
> +		      <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base)
> */
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure
> */
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical
> Non-Secure */
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
> +	};
> +
> +	frosc: clock-frosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <192000000>;
> +		clock-output-names = "frosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	lposc: clock-lposc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <1000000>;
> +		clock-output-names = "lposc";
> +		#clock-cells = <0>;
> +	};
> +
> +	rosc: clock-rosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32768>;
> +		clock-output-names = "rosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	sosc: clock-sosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <24000000>;
> +		clock-output-names = "sosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	soc@0 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x0 0x0 0x0 0x40000000>;
> +
> +		per_bridge3: bus@29000000 {
> +			compatible = "simple-bus";
> +			reg = <0x29000000 0x800000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			wdog3: watchdog@292a0000 {
> +				compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
> +				reg = <0x292a0000 0x10000>;
> +				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
> +				assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
> +				assigned-clocks-parents = <&cgc1
> IMX8ULP_CLK_SOSC_DIV2>;
> +				timeout-sec = <40>;
> +			};
> +
> +			cgc1: clock-controller@292c0000 {
> +				compatible = "fsl,imx8ulp-cgc1";
> +				reg = <0x292c0000 0x10000>;
> +				clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
> +				clock-names = "rosc", "sosc", "frosc", "lposc";
> +				#clock-cells = <1>;
> +			};
> +
> +			pcc3: clock-controller@292d0000 {
> +				compatible = "fsl,imx8ulp-pcc3";
> +				reg = <0x292d0000 0x10000>;
> +				#clock-cells = <1>;
> +			};
> +
> +			tpm5: tpm@29340000 {
> +				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
> +				reg = <0x29340000 0x1000>;
> +				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
> +					 <&pcc3 IMX8ULP_CLK_TPM5>;
> +				clock-names = "ipg", "per";
> +				status = "disabled";
> +			};
> +
> +			lpi2c4: i2c@29370000 {
> +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> +				reg = <0x29370000 0x10000>;
> +				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
> +					 <&pcc3 IMX8ULP_CLK_LPI2C4>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
> +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <48000000>;
> +				status = "disabled";
> +			};
> +
> +			lpi2c5: i2c@29380000 {
> +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> +				reg = <0x29380000 0x10000>;
> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
> +					 <&pcc3 IMX8ULP_CLK_LPI2C5>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
> +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <48000000>;
> +				status = "disabled";
> +			};
> +
> +			lpuart4: serial@29390000 {
> +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> +				reg = <0x29390000 0x1000>;
> +				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			lpuart5: serial@293a0000 {
> +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> +				reg = <0x293a0000 0x1000>;
> +				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			lpspi4: spi@293b0000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
> +				reg = <0x293b0000 0x10000>;
> +				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
> +					 <&pcc3 IMX8ULP_CLK_LPSPI4>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
> +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <16000000>;
> +				status = "disabled";
> +			};
> +
> +			lpspi5: spi@293c0000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
> +				reg = <0x293c0000 0x10000>;
> +				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
> +					 <&pcc3 IMX8ULP_CLK_LPSPI5>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
> +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <16000000>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		per_bridge4: bus@29800000 {
> +			compatible = "simple-bus";
> +			reg = <0x29800000 0x800000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			pcc4: clock-controller@29800000 {
> +				compatible = "fsl,imx8ulp-pcc4";
> +				reg = <0x29800000 0x10000>;
> +				#clock-cells = <1>;
> +			};
> +
> +			lpi2c6: i2c@29840000 {
> +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> +				reg = <0x29840000 0x10000>;
> +				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
> +					 <&pcc4 IMX8ULP_CLK_LPI2C6>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
> +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <48000000>;
> +				status = "disabled";
> +			};
> +
> +			lpi2c7: i2c@29850000 {
> +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> +				reg = <0x29850000 0x10000>;
> +				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
> +					 <&pcc4 IMX8ULP_CLK_LPI2C7>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
> +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <48000000>;
> +				status = "disabled";
> +			};
> +
> +			lpuart6: serial@29860000 {
> +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> +				reg = <0x29860000 0x1000>;
> +				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			lpuart7: serial@29870000 {
> +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> +				reg = <0x29870000 0x1000>;
> +				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			iomuxc1: pinctrl@298c0000 {
> +				compatible = "fsl,imx8ulp-iomuxc1";
> +				reg = <0x298c0000 0x10000>;
> +			};
> +
> +			usdhc0: mmc@298d0000 {
> +				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
> +				reg = <0x298d0000 0x10000>;
> +				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> +					 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
> +					 <&pcc4 IMX8ULP_CLK_USDHC0>;
> +				clock-names = "ipg", "ahb", "per";
> +				fsl,tuning-start-tap = <20>;
> +				fsl,tuning-step= <2>;
> +				bus-width = <4>;
> +				status = "disabled";
> +			};
> +
> +			usdhc1: mmc@298e0000 {
> +				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
> +				reg = <0x298e0000 0x10000>;
> +				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> +					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
> +					 <&pcc4 IMX8ULP_CLK_USDHC1>;
> +				clock-names = "ipg", "ahb", "per";
> +				fsl,tuning-start-tap = <20>;
> +				fsl,tuning-step= <2>;
> +				bus-width = <4>;
> +				status = "disabled";
> +			};
> +
> +			usdhc2: mmc@298f0000 {
> +				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
> +				reg = <0x298f0000 0x10000>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> +					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
> +					 <&pcc4 IMX8ULP_CLK_USDHC2>;
> +				clock-names = "ipg", "ahb", "per";
> +				fsl,tuning-start-tap = <20>;
> +				fsl,tuning-step= <2>;
> +				bus-width = <4>;
> +				status = "disabled";
> +			};
> +
> +			usbotg1: usb@29900000 {
> +				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
> "fsl,imx6ul-usb";
> +				reg = <0x29900000 0x200>;
> +				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_USB0>;
> +				phys = <&usbphy1>;
> +				fsl,usbmisc = <&usbmisc1 0>;
> +				ahb-burst-config = <0x0>;
> +				tx-burst-size-dword = <0x8>;
> +				rx-burst-size-dword = <0x8>;
> +				status = "disabled";
> +			};
> +
> +			usbmisc1: usbmisc@29900200 {
> +				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
> "fsl,imx7d-usbmisc";

I guess we can drop the oldest one if no special requirement

> +				#index-cells = <1>;
> +				reg = <0x29900200 0x200>;
> +				status = "disabled";
> +			};
> +
> +			usbphy1: usb-phy@29910000 {
> +				compatible = "fsl,imx7ulp-usbphy", "fsl,imx7ulp-usbphy",
> "fsl,imx6ul-usbphy";

Duplicated imx7ulp-usbphy?

> +				reg = <0x29910000 0x10000>;
> +				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			usbotg2: usb@29920000 {
> +				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
> "fsl,imx6ul-usb";

Ditto

Regards
Aisheng

> +				reg = <0x29920000 0x200>;
> +				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_USB1>;
> +				phys = <&usbphy2>;
> +				fsl,usbmisc = <&usbmisc2 0>;
> +				ahb-burst-config = <0x0>;
> +				tx-burst-size-dword = <0x8>;
> +				rx-burst-size-dword = <0x8>;
> +				status = "disabled";
> +			};
> +
> +			usbmisc2: usbmisc@29920200 {
> +				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
> "fsl,imx7d-usbmisc";
> +				#index-cells = <1>;
> +				reg = <0x29920200 0x200>;
> +				status = "disabled";
> +			};
> +
> +			usbphy2: usb-phy@29930000 {
> +				compatible = "fsl,imx7ulp-usbphy", "fsl,imx7ulp-usbphy",
> "fsl,imx6ul-usbphy";
> +				reg = <0x29930000 0x10000>;
> +				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			fec: ethernet@29950000 {
> +				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec";
> +				reg = <0x29950000 0x10000>;
> +				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "int0";
> +				clocks = <&pcc4 IMX8ULP_CLK_ENET>,
> +					 <&pcc4 IMX8ULP_CLK_ENET>,
> +					 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
> +				clock-names = "ipg", "ahb", "ptp";
> +				assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
> +				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC>;
> +				assigned-clock-rates = <24000000>;
> +				fsl,num-tx-queues = <1>;
> +				fsl,num-rx-queues = <1>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		gpioe: gpio@2d000000 {
> +				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
> +				reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
> +					 <&pcc4 IMX8ULP_CLK_PCTLE>;
> +				clock-names = "gpio", "port";
> +				gpio-ranges = <&iomuxc1 0 32 24>;
> +		};
> +
> +		gpiof: gpio@2d010000 {
> +				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
> +				reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
> +					 <&pcc4 IMX8ULP_CLK_PCTLF>;
> +				clock-names = "gpio", "port";
> +				gpio-ranges = <&iomuxc1 0 64 32>;
> +		};
> +
> +		per_bridge5: bus@2d800000 {
> +			compatible = "simple-bus";
> +			reg = <0x2d800000 0x800000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			cgc2: clock-controller@2da60000 {
> +				compatible = "fsl,imx8ulp-cgc2";
> +				reg = <0x2da60000 0x10000>;
> +				clocks = <&sosc>, <&frosc>;
> +				clock-names = "sosc", "frosc";
> +				#clock-cells = <1>;
> +			};
> +
> +			pcc5: clock-controller@2da70000 {
> +				compatible = "fsl,imx8ulp-pcc5";
> +				reg = <0x2da70000 0x10000>;
> +				#clock-cells = <1>;
> +			};
> +		};
> +
> +		gpiod: gpio@2e200000 {
> +			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
> +			reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
> +				 <&pcc5 IMX8ULP_CLK_RGPIOD>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 0 24>;
> +		};
> +	};
> +};
> --
> 2.26.2

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 11/11] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board
  2021-06-07  8:39 ` [PATCH 11/11] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board Jacky Bai
@ 2021-06-11 14:43   ` Dong Aisheng
  0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-06-11 14:43 UTC (permalink / raw)
  To: Jacky Bai
  Cc: Rob Herring, Shawn Guo, Stephen Boyd, Sascha Hauer,
	Linus Walleij, Dong Aisheng, Fabio Estevam, Sascha Hauer,
	dl-linux-imx, devicetree,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Mon, Jun 7, 2021 at 4:39 PM Jacky Bai <ping.bai@nxp.com> wrote:
>
> Add the basic dts file for i.MX8ULP EVK board.
> Only the necessary devices for minimal system boot up are enabled:
> enet, emmc, usb, console uart.
>
> some of the devices' pin status may lost during low power mode,
> so additional sleep pinctrl properties are included by default.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Mostly looks good

> ---
>  arch/arm64/boot/dts/freescale/Makefile        |   1 +
>  arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 143 ++++++++++++++++++
>  2 files changed, 144 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 25806c4924cb..8c24a05d55af 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -65,5 +65,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
>
>  dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> new file mode 100644
> index 000000000000..f4db04f357fe
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8ulp.dtsi"
> +
> +/ {
> +       model = "NXP i.MX8ULP EVK";
> +       compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
> +
> +       chosen {
> +               stdout-path = &lpuart5;
> +       };

no memory node?

Regards
Aisheng

> +};
> +
> +&fec {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_enet>;
> +       phy-mode = "rmii";
> +       phy-handle = <&ethphy>;
> +       status = "okay";
> +
> +       mdio {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               ethphy: ethernet-phy {
> +                       reg = <1>;
> +                       micrel,led-mode = <1>;
> +               };
> +       };
> +};
> +
> +&lpuart5 {
> +       /* console */
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&pinctrl_lpuart5>;
> +       pinctrl-1 = <&pinctrl_lpuart5>;
> +       status = "okay";
> +};
> +
> +&usbotg1 {
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&pinctrl_otgid1>;
> +       pinctrl-1 = <&pinctrl_otgid1>;
> +       dr_mode = "otg";
> +       hnp-disable;
> +       srp-disable;
> +       adp-disable;
> +       status = "okay";
> +};
> +
> +&usbphy1 {
> +       status = "okay";
> +};
> +
> +&usbmisc1 {
> +       status = "okay";
> +};
> +
> +&usbotg2 {
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&pinctrl_otgid2>;
> +       pinctrl-1 = <&pinctrl_otgid2>;
> +       dr_mode = "otg";
> +       hnp-disable;
> +       srp-disable;
> +       adp-disable;
> +       status = "okay";
> +};
> +
> +&usbphy2 {
> +       status = "okay";
> +};
> +
> +&usbmisc2 {
> +       status = "okay";
> +};
> +
> +&usdhc0 {
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&pinctrl_usdhc0>;
> +       pinctrl-1 = <&pinctrl_usdhc0>;
> +       non-removable;
> +       bus-width = <4>;
> +       status = "okay";
> +};
> +
> +&iomuxc1 {
> +       pinctrl_enet: enetgrp {
> +               fsl,pins = <
> +                       MX8ULP_PAD_PTE15__ENET0_MDC     0x43
> +                       MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
> +                       MX8ULP_PAD_PTE17__ENET0_RXER    0x43
> +                       MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
> +                       MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
> +                       MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
> +                       MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
> +                       MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
> +                       MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
> +                       MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
> +                       MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
> +               >;
> +       };
> +
> +       pinctrl_lpuart5: lpuart5grp {
> +               fsl,pins = <
> +                       MX8ULP_PAD_PTF14__LPUART5_TX    0x3
> +                       MX8ULP_PAD_PTF15__LPUART5_RX    0x3
> +               >;
> +       };
> +
> +       pinctrl_otgid1: usb1grp {
> +               fsl,pins = <
> +                       MX8ULP_PAD_PTF2__USB0_ID        0x10003
> +               >;
> +       };
> +
> +       pinctrl_otgid2: usb2grp {
> +               fsl,pins = <
> +                       MX8ULP_PAD_PTD23__USB1_ID       0x10003
> +               >;
> +       };
> +
> +       pinctrl_usdhc0: usdhc0grp {
> +               fsl,pins = <
> +                       MX8ULP_PAD_PTD1__SDHC0_CMD      0x43
> +                       MX8ULP_PAD_PTD2__SDHC0_CLK      0x10042
> +                       MX8ULP_PAD_PTD10__SDHC0_D0      0x43
> +                       MX8ULP_PAD_PTD9__SDHC0_D1       0x43
> +                       MX8ULP_PAD_PTD8__SDHC0_D2       0x43
> +                       MX8ULP_PAD_PTD7__SDHC0_D3       0x43
> +                       MX8ULP_PAD_PTD6__SDHC0_D4       0x43
> +                       MX8ULP_PAD_PTD5__SDHC0_D5       0x43
> +                       MX8ULP_PAD_PTD4__SDHC0_D6       0x43
> +                       MX8ULP_PAD_PTD3__SDHC0_D7       0x43
> +                       MX8ULP_PAD_PTD11__SDHC0_DQS     0x10042
> +               >;
> +       };
> +};
> --
> 2.26.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
  2021-06-09 10:56   ` Linus Walleij
  2021-06-11 13:45   ` Dong Aisheng
@ 2021-06-16 23:42   ` Rob Herring
  2 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2021-06-16 23:42 UTC (permalink / raw)
  To: Jacky Bai
  Cc: shawnguo, robh+dt, festevam, s.hauer, linus.walleij,
	aisheng.dong, sboyd, linux-imx, devicetree, kernel,
	linux-arm-kernel

On Mon, 07 Jun 2021 16:39:11 +0800, Jacky Bai wrote:
> Add the compatible string for i.MX8ULP.
> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  Documentation/devicetree/bindings/gpio/gpio-vf610.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 02/11] dt-bindings: i2c: imx-lpi2c: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 02/11] dt-bindings: i2c: imx-lpi2c: " Jacky Bai
  2021-06-11 13:46   ` Dong Aisheng
@ 2021-06-16 23:43   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Rob Herring @ 2021-06-16 23:43 UTC (permalink / raw)
  To: Jacky Bai
  Cc: linus.walleij, linux-arm-kernel, devicetree, kernel, shawnguo,
	festevam, linux-imx, s.hauer, aisheng.dong, robh+dt, sboyd

On Mon, 07 Jun 2021 16:39:12 +0800, Jacky Bai wrote:
> Add the compatible for i.MX8ULP.
> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 03/11] dt-bindings: mmc: imx-esdhc: Add imx8ulp compatibe string
  2021-06-07  8:39 ` [PATCH 03/11] dt-bindings: mmc: imx-esdhc: Add imx8ulp compatibe string Jacky Bai
  2021-06-11 13:50   ` Dong Aisheng
@ 2021-06-16 23:44   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Rob Herring @ 2021-06-16 23:44 UTC (permalink / raw)
  To: Jacky Bai
  Cc: shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong, festevam,
	kernel, linux-imx, devicetree, linux-arm-kernel

On Mon, Jun 07, 2021 at 04:39:13PM +0800, Jacky Bai wrote:
> For i.MX8ULP, it uses two compatible strings, so update
> the compatible string for i.MX8ULP.

typo in the subject

> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 4 ++++
>  1 file changed, 4 insertions(+)

Otherwise,

Acked-by: Rob Herring <robh@kernel.org>

> 
> diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
> index 369471814496..aeee2be1e36a 100644
> --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
> @@ -42,6 +42,10 @@ properties:
>                - fsl,imx8qm-usdhc
>                - fsl,imx8qxp-usdhc
>            - const: fsl,imx7d-usdhc
> +      - items:
> +          - enum:
> +              - fsl,imx8ulp-usdhc
> +          - const: fsl,imx8mm-usdhc
>  
>    reg:
>      maxItems: 1
> -- 
> 2.26.2

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 04/11] dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 04/11] dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string Jacky Bai
  2021-06-11 13:52   ` Dong Aisheng
@ 2021-06-16 23:44   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Rob Herring @ 2021-06-16 23:44 UTC (permalink / raw)
  To: Jacky Bai
  Cc: aisheng.dong, robh+dt, linus.walleij, devicetree,
	linux-arm-kernel, shawnguo, s.hauer, festevam, sboyd, linux-imx,
	kernel

On Mon, 07 Jun 2021 16:39:14 +0800, Jacky Bai wrote:
> For i.MX8ULP, it uses two compatible strings, so Update the
> compatible string for i.MX8ULP.
> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 05/11] dt-bindings: spi: fsl-lpspi: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 05/11] dt-bindings: spi: fsl-lpspi: " Jacky Bai
  2021-06-11 13:57   ` Dong Aisheng
@ 2021-06-16 23:45   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Rob Herring @ 2021-06-16 23:45 UTC (permalink / raw)
  To: Jacky Bai
  Cc: shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong, festevam,
	kernel, linux-imx, devicetree, linux-arm-kernel

On Mon, Jun 07, 2021 at 04:39:15PM +0800, Jacky Bai wrote:
> For i.MX8ULP, it uses two compatible strings, so update the
> comaptible strings.

typo here.

> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  .../devicetree/bindings/spi/spi-fsl-lpspi.yaml        | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 06/11] dt-bindings: timer: tpm-timer: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 06/11] dt-bindings: timer: tpm-timer: " Jacky Bai
  2021-06-11 13:58   ` Dong Aisheng
@ 2021-06-16 23:45   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Rob Herring @ 2021-06-16 23:45 UTC (permalink / raw)
  To: Jacky Bai
  Cc: shawnguo, s.hauer, linux-imx, devicetree, robh+dt, sboyd,
	linux-arm-kernel, festevam, linus.walleij, aisheng.dong, kernel

On Mon, 07 Jun 2021 16:39:16 +0800, Jacky Bai wrote:
> For i.MX8ULP, it use two compatible strings, so update the
> compatible strings for it.
> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 07/11] dt-bindings: watchdog: imx7ulp-wdt: Add imx8ulp compatible string
  2021-06-07  8:39 ` [PATCH 07/11] dt-bindings: watchdog: imx7ulp-wdt: " Jacky Bai
  2021-06-11 13:58   ` Dong Aisheng
@ 2021-06-16 23:45   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Rob Herring @ 2021-06-16 23:45 UTC (permalink / raw)
  To: Jacky Bai
  Cc: kernel, festevam, linux-imx, devicetree, aisheng.dong, shawnguo,
	linus.walleij, s.hauer, sboyd, robh+dt, linux-arm-kernel

On Mon, 07 Jun 2021 16:39:17 +0800, Jacky Bai wrote:
> For i.MX8ULP, it uses two compatible strings, so Add the compatible
> string for i.MX8ULP.
> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  .../devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml      | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk
  2021-06-07  8:39 ` [PATCH 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk Jacky Bai
  2021-06-11 13:59   ` Dong Aisheng
@ 2021-06-16 23:46   ` Rob Herring
  1 sibling, 0 replies; 36+ messages in thread
From: Rob Herring @ 2021-06-16 23:46 UTC (permalink / raw)
  To: Jacky Bai
  Cc: linux-arm-kernel, festevam, linux-imx, linus.walleij,
	aisheng.dong, kernel, sboyd, s.hauer, shawnguo, robh+dt,
	devicetree

On Mon, 07 Jun 2021 16:39:18 +0800, Jacky Bai wrote:
> Add the dt binding for i.MX8ULP EVK board.
> 
> i.MX 8ULP is part of the ULP family with emphasis on extreme
> low-power techniques using the 28 nm fully depleted silicon on
> insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
> based on asymmetric architecture, however will add a third DSP
> domain for advanced voice/audio capability and a Graphics domain
> where it is possible to access graphics resources from the
> application side or the realtime side.
> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 09/11] dt-bindings: clock: Add imx8ulp clock support
  2021-06-07  8:39 ` [PATCH 09/11] dt-bindings: clock: Add imx8ulp clock support Jacky Bai
  2021-06-11 14:17   ` Dong Aisheng
@ 2021-06-16 23:47   ` Rob Herring
  2021-06-17  9:09     ` Jacky Bai
  1 sibling, 1 reply; 36+ messages in thread
From: Rob Herring @ 2021-06-16 23:47 UTC (permalink / raw)
  To: Jacky Bai
  Cc: shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong, festevam,
	kernel, linux-imx, devicetree, linux-arm-kernel

On Mon, Jun 07, 2021 at 04:39:19PM +0800, Jacky Bai wrote:
> Add the clock dt-binding file for i.MX8ULP.
> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  .../bindings/clock/imx8ulp-clock.yaml         |  72 +++++
>  include/dt-bindings/clock/imx8ulp-clock.h     | 261 ++++++++++++++++++
>  2 files changed, 333 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
>  create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> new file mode 100644
> index 000000000000..ffe7b713d4e7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: GPL-2.0

Dual license new bindings.

> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/imx8ulp-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8ULP Clock Control Module Binding
> +
> +maintainers:
> +  - Jacky Bai <ping.bai@nxp.com>
> +
> +description: |
> +  On i.MX8ULP, The clock sources generation, distribution and management is
> +  under the control of several CGCs & PCCs modules. The CGC modules generate
> +  and distribute clocks on the device. PCC modules control clock selection,
> +  optional division and clock gating mode for peripherals
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx8ulp-cgc1
> +      - fsl,imx8ulp-cgc2
> +      - fsl,imx8ulp-pcc3
> +      - fsl,imx8ulp-pcc4
> +      - fsl,imx8ulp-pcc5
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    description:
> +      specify the external clocks used by the CGC module, the clocks
> +      are rosc, sosc, frosc, lposc
> +    maxItems: 4
> +
> +  clock-names:
> +    description:
> +      specify the external clocks names used by the CGC module. the valid
> +      clock names should rosc, sosc, frosc, lposc.
> +    maxItems: 4
> +
> +  '#clock-cells':
> +    const: 1
> +    description:
> +      The clock consumer should specify the desired clock by having the clock
> +      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8ulp-clock.h
> +      for the full list of i.MX8ULP clock IDs.
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock Control Module node:
> +  - |
> +    clock-controller@292c0000 {
> +        compatible = "fsl,imx8ulp-cgc1";
> +        reg = <0x292c0000 0x10000>;
> +        clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
> +        clock-names = "rosc", "sosc", "frosc", "lposc";
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    clock-controller@292d0000 {
> +        compatible = "fsl,imx8ulp-pcc3";
> +        reg = <0x292d0000 0x10000>;
> +        #clock-cells = <1>;
> +    };
> diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
> new file mode 100644
> index 000000000000..61518775f434
> --- /dev/null
> +++ b/include/dt-bindings/clock/imx8ulp-clock.h
> @@ -0,0 +1,261 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Dual license please.

> +/*
> + * Copyright 2021 NXP
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
> +#define __DT_BINDINGS_CLOCK_IMX8ULP_H
> +
> +#define IMX8ULP_CLK_DUMMY			0
> +#define IMX8ULP_CLK_ROSC			1
> +#define IMX8ULP_CLK_FROSC			2
> +#define IMX8ULP_CLK_LPOSC			3
> +#define IMX8ULP_CLK_SOSC			4
> +
> +/* CGC1 */
> +#define IMX8ULP_CLK_SPLL2			5
> +#define IMX8ULP_CLK_SPLL3			6
> +#define IMX8ULP_CLK_A35_SEL			7
> +#define IMX8ULP_CLK_A35_DIV			8
> +#define IMX8ULP_CLK_SPLL2_PRE_SEL		9
> +#define IMX8ULP_CLK_SPLL3_PRE_SEL		10
> +#define IMX8ULP_CLK_SPLL3_PFD0			11
> +#define IMX8ULP_CLK_SPLL3_PFD1			12
> +#define IMX8ULP_CLK_SPLL3_PFD2			13
> +#define IMX8ULP_CLK_SPLL3_PFD3			14
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1		15
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2		16
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1		17
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2		18
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1		19
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2		20
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1		21
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2		22
> +#define IMX8ULP_CLK_NIC_SEL			23
> +#define IMX8ULP_CLK_NIC_AD_DIVPLAT		24
> +#define IMX8ULP_CLK_NIC_PER_DIVPLAT		25
> +#define IMX8ULP_CLK_XBAR_SEL			26
> +#define IMX8ULP_CLK_XBAR_AD_DIVPLAT		27
> +#define IMX8ULP_CLK_XBAR_DIVBUS			28
> +#define IMX8ULP_CLK_XBAR_AD_SLOW		29
> +#define IMX8ULP_CLK_SOSC_DIV1			30
> +#define IMX8ULP_CLK_SOSC_DIV2			31
> +#define IMX8ULP_CLK_SOSC_DIV3			32
> +#define IMX8ULP_CLK_FROSC_DIV1			33
> +#define IMX8ULP_CLK_FROSC_DIV2			34
> +#define IMX8ULP_CLK_FROSC_DIV3			35
> +#define IMX8ULP_CLK_SPLL3_VCODIV		36
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE	37
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE	38
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE	39
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE	40
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE	41
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE	42
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE	43
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE	44
> +#define IMX8ULP_CLK_SOSC_DIV1_GATE		45
> +#define IMX8ULP_CLK_SOSC_DIV2_GATE		46
> +#define IMX8ULP_CLK_SOSC_DIV3_GATE		47
> +#define IMX8ULP_CLK_FROSC_DIV1_GATE		48
> +#define IMX8ULP_CLK_FROSC_DIV2_GATE		49
> +#define IMX8ULP_CLK_FROSC_DIV3_GATE		50
> +#define IMX8ULP_CLK_SAI4_SEL			51
> +#define IMX8ULP_CLK_SAI5_SEL			52
> +#define IMX8ULP_CLK_AUD_CLK1			53
> +#define IMX8ULP_CLK_ARM				54
> +#define IMX8ULP_CLK_ENET_TS_SEL			55
> +
> +#define IMX8ULP_CLK_CGC1_END			56
> +
> +/* CGC2 */
> +#define IMX8ULP_CLK_PLL4_PRE_SEL	0
> +#define IMX8ULP_CLK_PLL4		1
> +#define IMX8ULP_CLK_PLL4_VCODIV		2
> +#define IMX8ULP_CLK_DDR_SEL		3
> +#define IMX8ULP_CLK_DDR_DIV		4
> +#define IMX8ULP_CLK_LPAV_AXI_SEL	5
> +#define IMX8ULP_CLK_LPAV_AXI_DIV	6
> +#define IMX8ULP_CLK_LPAV_AHB_DIV	7
> +#define IMX8ULP_CLK_LPAV_BUS_DIV	8
> +#define IMX8ULP_CLK_PLL4_PFD0		9
> +#define IMX8ULP_CLK_PLL4_PFD1		10
> +#define IMX8ULP_CLK_PLL4_PFD2		11
> +#define IMX8ULP_CLK_PLL4_PFD3		12
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE	13
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE	14
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE	15
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE	16
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE	17
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE	18
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE	19
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE	20
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV1	21
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV2	22
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV1	23
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV2	24
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV1	25
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV2	26
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV1	27
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV2	28
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE	29
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE	30
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE	31
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV1	32
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV2	33
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV3	34
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE	35
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE	36
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE	37
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV1	38
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV2	39
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV3	40
> +#define IMX8ULP_CLK_AUD_CLK2		41
> +#define IMX8ULP_CLK_SAI6_SEL		42
> +#define IMX8ULP_CLK_SAI7_SEL		43
> +#define IMX8ULP_CLK_SPDIF_SEL		44
> +#define IMX8ULP_CLK_HIFI_SEL		45
> +#define IMX8ULP_CLK_HIFI_DIVCORE	46
> +#define IMX8ULP_CLK_HIFI_DIVPLAT	47
> +#define IMX8ULP_CLK_DSI_PHY_REF		48
> +
> +#define IMX8ULP_CLK_CGC2_END		49
> +
> +/* PCC3 */
> +#define IMX8ULP_CLK_WDOG3		0
> +#define IMX8ULP_CLK_WDOG4		1
> +#define IMX8ULP_CLK_LPIT1		2
> +#define IMX8ULP_CLK_TPM4		3
> +#define IMX8ULP_CLK_TPM5		4
> +#define IMX8ULP_CLK_FLEXIO1		5
> +#define IMX8ULP_CLK_I3C2		6
> +#define IMX8ULP_CLK_LPI2C4		7
> +#define IMX8ULP_CLK_LPI2C5		8
> +#define IMX8ULP_CLK_LPUART4		9
> +#define IMX8ULP_CLK_LPUART5		10
> +#define IMX8ULP_CLK_LPSPI4		11
> +#define IMX8ULP_CLK_LPSPI5		12
> +#define IMX8ULP_CLK_DMA1_MP		13
> +#define IMX8ULP_CLK_DMA1_CH0		14
> +#define IMX8ULP_CLK_DMA1_CH1		15
> +#define IMX8ULP_CLK_DMA1_CH2		16
> +#define IMX8ULP_CLK_DMA1_CH3		17
> +#define IMX8ULP_CLK_DMA1_CH4		18
> +#define IMX8ULP_CLK_DMA1_CH5		19
> +#define IMX8ULP_CLK_DMA1_CH6		20
> +#define IMX8ULP_CLK_DMA1_CH7		21
> +#define IMX8ULP_CLK_DMA1_CH8		22
> +#define IMX8ULP_CLK_DMA1_CH9		23
> +#define IMX8ULP_CLK_DMA1_CH10		24
> +#define IMX8ULP_CLK_DMA1_CH11		25
> +#define IMX8ULP_CLK_DMA1_CH12		26
> +#define IMX8ULP_CLK_DMA1_CH13		27
> +#define IMX8ULP_CLK_DMA1_CH14		28
> +#define IMX8ULP_CLK_DMA1_CH15		29
> +#define IMX8ULP_CLK_DMA1_CH16		30
> +#define IMX8ULP_CLK_DMA1_CH17		31
> +#define IMX8ULP_CLK_DMA1_CH18		32
> +#define IMX8ULP_CLK_DMA1_CH19		33
> +#define IMX8ULP_CLK_DMA1_CH20		34
> +#define IMX8ULP_CLK_DMA1_CH21		35
> +#define IMX8ULP_CLK_DMA1_CH22		36
> +#define IMX8ULP_CLK_DMA1_CH23		37
> +#define IMX8ULP_CLK_DMA1_CH24		38
> +#define IMX8ULP_CLK_DMA1_CH25		39
> +#define IMX8ULP_CLK_DMA1_CH26		40
> +#define IMX8ULP_CLK_DMA1_CH27		41
> +#define IMX8ULP_CLK_DMA1_CH28		42
> +#define IMX8ULP_CLK_DMA1_CH29		43
> +#define IMX8ULP_CLK_DMA1_CH30		44
> +#define IMX8ULP_CLK_DMA1_CH31		45
> +#define IMX8ULP_CLK_MU3_A		46
> +
> +#define IMX8ULP_CLK_PCC3_END		47
> +
> +/* PCC4 */
> +#define IMX8ULP_CLK_FLEXSPI2		0
> +#define IMX8ULP_CLK_TPM6		1
> +#define IMX8ULP_CLK_TPM7		2
> +#define IMX8ULP_CLK_LPI2C6		3
> +#define IMX8ULP_CLK_LPI2C7		4
> +#define IMX8ULP_CLK_LPUART6		5
> +#define IMX8ULP_CLK_LPUART7		6
> +#define IMX8ULP_CLK_SAI4		7
> +#define IMX8ULP_CLK_SAI5		8
> +#define IMX8ULP_CLK_PCTLE		9
> +#define IMX8ULP_CLK_PCTLF		10
> +#define IMX8ULP_CLK_USDHC0		11
> +#define IMX8ULP_CLK_USDHC1		12
> +#define IMX8ULP_CLK_USDHC2		13
> +#define IMX8ULP_CLK_USB0		14
> +#define IMX8ULP_CLK_USB0_PHY		15
> +#define IMX8ULP_CLK_USB1		16
> +#define IMX8ULP_CLK_USB1_PHY		17
> +#define IMX8ULP_CLK_USB_XBAR		18
> +#define IMX8ULP_CLK_ENET		19
> +#define IMX8ULP_CLK_SFA1		20
> +#define IMX8ULP_CLK_RGPIOE		21
> +#define IMX8ULP_CLK_RGPIOF		22
> +
> +#define IMX8ULP_CLK_PCC4_END		23
> +
> +/* PCC5 */
> +#define IMX8ULP_CLK_TPM8		0
> +#define IMX8ULP_CLK_SAI6		1
> +#define IMX8ULP_CLK_SAI7		2
> +#define IMX8ULP_CLK_SPDIF		3
> +#define IMX8ULP_CLK_ISI			4
> +#define IMX8ULP_CLK_CSI_REGS 		5
> +#define IMX8ULP_CLK_PCTLD		6
> +#define IMX8ULP_CLK_CSI			7
> +#define IMX8ULP_CLK_DSI			8
> +#define IMX8ULP_CLK_WDOG5		9
> +#define IMX8ULP_CLK_EPDC		10
> +#define IMX8ULP_CLK_PXP			11
> +#define IMX8ULP_CLK_SFA2		12
> +#define IMX8ULP_CLK_GPU2D		13
> +#define IMX8ULP_CLK_GPU3D		14
> +#define IMX8ULP_CLK_DC_NANO		15
> +#define IMX8ULP_CLK_CSI_CLK_UI 		16
> +#define IMX8ULP_CLK_CSI_CLK_ESC		17
> +#define IMX8ULP_CLK_RGPIOD		18
> +#define IMX8ULP_CLK_DMA2_MP		19
> +#define IMX8ULP_CLK_DMA2_CH0		20
> +#define IMX8ULP_CLK_DMA2_CH1		21
> +#define IMX8ULP_CLK_DMA2_CH2		22
> +#define IMX8ULP_CLK_DMA2_CH3		23
> +#define IMX8ULP_CLK_DMA2_CH4		24
> +#define IMX8ULP_CLK_DMA2_CH5		25
> +#define IMX8ULP_CLK_DMA2_CH6		26
> +#define IMX8ULP_CLK_DMA2_CH7		27
> +#define IMX8ULP_CLK_DMA2_CH8		28
> +#define IMX8ULP_CLK_DMA2_CH9		29
> +#define IMX8ULP_CLK_DMA2_CH10		30
> +#define IMX8ULP_CLK_DMA2_CH11		31
> +#define IMX8ULP_CLK_DMA2_CH12		32
> +#define IMX8ULP_CLK_DMA2_CH13		33
> +#define IMX8ULP_CLK_DMA2_CH14		34
> +#define IMX8ULP_CLK_DMA2_CH15		35
> +#define IMX8ULP_CLK_DMA2_CH16		36
> +#define IMX8ULP_CLK_DMA2_CH17		37
> +#define IMX8ULP_CLK_DMA2_CH18		38
> +#define IMX8ULP_CLK_DMA2_CH19		39
> +#define IMX8ULP_CLK_DMA2_CH20		40
> +#define IMX8ULP_CLK_DMA2_CH21		41
> +#define IMX8ULP_CLK_DMA2_CH22		42
> +#define IMX8ULP_CLK_DMA2_CH23		43
> +#define IMX8ULP_CLK_DMA2_CH24		44
> +#define IMX8ULP_CLK_DMA2_CH25		45
> +#define IMX8ULP_CLK_DMA2_CH26		46
> +#define IMX8ULP_CLK_DMA2_CH27		47
> +#define IMX8ULP_CLK_DMA2_CH28		48
> +#define IMX8ULP_CLK_DMA2_CH29		49
> +#define IMX8ULP_CLK_DMA2_CH30		50
> +#define IMX8ULP_CLK_DMA2_CH31		51
> +#define IMX8ULP_CLK_MU2_B		52
> +#define IMX8ULP_CLK_MU3_B		53
> +#define IMX8ULP_CLK_AVD_SIM		54
> +#define IMX8ULP_CLK_DSI_TX_ESC		55
> +
> +#define IMX8ULP_CLK_PCC5_END		56
> +
> +#endif
> -- 
> 2.26.2

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 10/11] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp
       [not found] ` <20210607083921.2668568-11-ping.bai@nxp.com>
  2021-06-11 14:40   ` [PATCH 10/11] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp Aisheng Dong
@ 2021-06-16 23:51   ` Rob Herring
  2021-06-17  9:03     ` Jacky Bai
  1 sibling, 1 reply; 36+ messages in thread
From: Rob Herring @ 2021-06-16 23:51 UTC (permalink / raw)
  To: Jacky Bai
  Cc: shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong, festevam,
	kernel, linux-imx, devicetree, linux-arm-kernel

On Mon, Jun 07, 2021 at 04:39:20PM +0800, Jacky Bai wrote:
> Add the basic dtsi support for i.MX8ULP.
> 
> i.MX 8ULP is part of the ULP family with emphasis on extreme
> low-power techniques using the 28 nm fully depleted silicon on
> insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
> based on asymmetric architecture, however will add a third DSP
> domain for advanced voice/audio capability and a Graphics domain
> where it is possible to access graphics resources from the
> application side or the realtime side.
> 
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
>  .../boot/dts/freescale/imx8ulp-pinfunc.h      | 978 ++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx8ulp.dtsi    | 474 +++++++++
>  2 files changed, 1452 insertions(+)
>  create mode 100755 arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> new file mode 100755
> index 000000000000..faa702634a38
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> @@ -0,0 +1,978 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */


> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> new file mode 100644
> index 000000000000..469c2dcd4636
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> @@ -0,0 +1,474 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

How can I use MIT when GPL only header is included? Dual license the 
header please.

And NXP is good with GPLv3, GPLv4, etc.?

> +/*
> + * Copyright 2021 NXP
> + */
> +
> +#include <dt-bindings/clock/imx8ulp-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "imx8ulp-pinfunc.h"

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^ permalink raw reply	[flat|nested] 36+ messages in thread

* RE: [PATCH 10/11] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp
  2021-06-16 23:51   ` Rob Herring
@ 2021-06-17  9:03     ` Jacky Bai
  2021-06-18  1:41       ` Jacky Bai
  0 siblings, 1 reply; 36+ messages in thread
From: Jacky Bai @ 2021-06-17  9:03 UTC (permalink / raw)
  To: Rob Herring
  Cc: shawnguo, sboyd, s.hauer, linus.walleij, Aisheng Dong, festevam,
	kernel, dl-linux-imx, devicetree, linux-arm-kernel

> Subject: Re: [PATCH 10/11] arm64: dts: imx8ulp: Add the basic dtsi file for
> imx8ulp
> 
> On Mon, Jun 07, 2021 at 04:39:20PM +0800, Jacky Bai wrote:
> > Add the basic dtsi support for i.MX8ULP.
> >
> > i.MX 8ULP is part of the ULP family with emphasis on extreme low-power
> > techniques using the 28 nm fully depleted silicon on insulator
> > process. Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric
> > architecture, however will add a third DSP domain for advanced
> > voice/audio capability and a Graphics domain where it is possible to
> > access graphics resources from the application side or the realtime
> > side.
> >
> > Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> > ---
> >  .../boot/dts/freescale/imx8ulp-pinfunc.h      | 978
> ++++++++++++++++++
> >  arch/arm64/boot/dts/freescale/imx8ulp.dtsi    | 474 +++++++++
> >  2 files changed, 1452 insertions(+)
> >  create mode 100755 arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> >  create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> > b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> > new file mode 100755
> > index 000000000000..faa702634a38
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> > @@ -0,0 +1,978 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> 
> 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > new file mode 100644
> > index 000000000000..469c2dcd4636
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > @@ -0,0 +1,474 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> 
> How can I use MIT when GPL only header is included? Dual license the header
> please.
> 

Ok, will add Dual license in the above file.

> And NXP is good with GPLv3, GPLv4, etc.?

It seems no file use GPLv3 in latest kernel, I will keep use GPLv2 for now, is it ok?

BR
Jacky Bai
> 
> > +/*
> > + * Copyright 2021 NXP
> > + */
> > +
> > +#include <dt-bindings/clock/imx8ulp-clock.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +#include "imx8ulp-pinfunc.h"
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^ permalink raw reply	[flat|nested] 36+ messages in thread

* RE: [PATCH 09/11] dt-bindings: clock: Add imx8ulp clock support
  2021-06-16 23:47   ` Rob Herring
@ 2021-06-17  9:09     ` Jacky Bai
  0 siblings, 0 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-17  9:09 UTC (permalink / raw)
  To: Rob Herring
  Cc: shawnguo, sboyd, s.hauer, linus.walleij, Aisheng Dong, festevam,
	kernel, dl-linux-imx, devicetree, linux-arm-kernel

> Subject: Re: [PATCH 09/11] dt-bindings: clock: Add imx8ulp clock support
> 
> On Mon, Jun 07, 2021 at 04:39:19PM +0800, Jacky Bai wrote:
> > Add the clock dt-binding file for i.MX8ULP.
> >
> > Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> > ---
> >  .../bindings/clock/imx8ulp-clock.yaml         |  72 +++++
> >  include/dt-bindings/clock/imx8ulp-clock.h     | 261
> ++++++++++++++++++
> >  2 files changed, 333 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> >  create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h
> >
> > diff --git
> > a/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> > b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> > new file mode 100644
> > index 000000000000..ffe7b713d4e7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> > @@ -0,0 +1,72 @@
> > +# SPDX-License-Identifier: GPL-2.0
> 
> Dual license new bindings.

Ok, will fix it.

BR

...
> > +
> > +title: NXP i.MX8ULP Clock Control Module Binding
> > +
> > +maintainers:
> > +  - Jacky Bai <ping.bai@nxp.com>
> > +
> > +description: |
> > +  On i.MX8ULP, The clock sources generation, distribution and
> > +management is
> > +  under the control of several CGCs & PCCs modules. The CGC modules
> > +generate
> > +  and distribute clocks on the device. PCC modules control clock
> > +selection,
> > +  optional division and clock gating mode for peripherals
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - fsl,imx8ulp-cgc1
> > +      - fsl,imx8ulp-cgc2
> > +      - fsl,imx8ulp-pcc3
> > +      - fsl,imx8ulp-pcc4
> > +      - fsl,imx8ulp-pcc5
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    description:
> > +      specify the external clocks used by the CGC module, the clocks
> > +      are rosc, sosc, frosc, lposc
> > +    maxItems: 4
> > +
> > +  clock-names:
> > +    description:
> > +      specify the external clocks names used by the CGC module. the
> valid
> > +      clock names should rosc, sosc, frosc, lposc.
> > +    maxItems: 4
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +    description:
> > +      The clock consumer should specify the desired clock by having the
> clock
> > +      ID in its "clocks" phandle cell. See
> include/dt-bindings/clock/imx8ulp-clock.h
> > +      for the full list of i.MX8ULP clock IDs.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  # Clock Control Module node:
> > +  - |
> > +    clock-controller@292c0000 {
> > +        compatible = "fsl,imx8ulp-cgc1";
> > +        reg = <0x292c0000 0x10000>;
> > +        clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
> > +        clock-names = "rosc", "sosc", "frosc", "lposc";
> > +        #clock-cells = <1>;
> > +    };
> > +
> > +  - |
> > +    clock-controller@292d0000 {
> > +        compatible = "fsl,imx8ulp-pcc3";
> > +        reg = <0x292d0000 0x10000>;
> > +        #clock-cells = <1>;
> > +    };
> > diff --git a/include/dt-bindings/clock/imx8ulp-clock.h
> > b/include/dt-bindings/clock/imx8ulp-clock.h
> > new file mode 100644
> > index 000000000000..61518775f434
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/imx8ulp-clock.h
> > @@ -0,0 +1,261 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> 
> Dual license please.

Ok, will fix it.

BR
Jacky Bai

> 
> > +/*
> > + * Copyright 2021 NXP
> > + */
> > +
> > +#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H #define
> > +__DT_BINDINGS_CLOCK_IMX8ULP_H
> > +
> > +#define IMX8ULP_CLK_DUMMY			0
> > +#define IMX8ULP_CLK_ROSC			1
> > +#define IMX8ULP_CLK_FROSC			2
> > +#define IMX8ULP_CLK_LPOSC			3
> > +#define IMX8ULP_CLK_SOSC			4
> > +
> > +/* CGC1 */
> > +#define IMX8ULP_CLK_SPLL2			5
> > +#define IMX8ULP_CLK_SPLL3			6
> > +#define IMX8ULP_CLK_A35_SEL			7
> > +#define IMX8ULP_CLK_A35_DIV			8
> > +#define IMX8ULP_CLK_SPLL2_PRE_SEL		9
> > +#define IMX8ULP_CLK_SPLL3_PRE_SEL		10
> > +#define IMX8ULP_CLK_SPLL3_PFD0			11
> > +#define IMX8ULP_CLK_SPLL3_PFD1			12
> > +#define IMX8ULP_CLK_SPLL3_PFD2			13
> > +#define IMX8ULP_CLK_SPLL3_PFD3			14
> > +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1		15
> > +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2		16
> > +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1		17
> > +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2		18
> > +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1		19
> > +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2		20
> > +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1		21
> > +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2		22
> > +#define IMX8ULP_CLK_NIC_SEL			23
> > +#define IMX8ULP_CLK_NIC_AD_DIVPLAT		24
> > +#define IMX8ULP_CLK_NIC_PER_DIVPLAT		25
> > +#define IMX8ULP_CLK_XBAR_SEL			26
> > +#define IMX8ULP_CLK_XBAR_AD_DIVPLAT		27
> > +#define IMX8ULP_CLK_XBAR_DIVBUS			28
> > +#define IMX8ULP_CLK_XBAR_AD_SLOW		29
> > +#define IMX8ULP_CLK_SOSC_DIV1			30
> > +#define IMX8ULP_CLK_SOSC_DIV2			31
> > +#define IMX8ULP_CLK_SOSC_DIV3			32
> > +#define IMX8ULP_CLK_FROSC_DIV1			33
> > +#define IMX8ULP_CLK_FROSC_DIV2			34
> > +#define IMX8ULP_CLK_FROSC_DIV3			35
> > +#define IMX8ULP_CLK_SPLL3_VCODIV		36
> > +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE	37
> > +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE	38
> > +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE	39
> > +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE	40
> > +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE	41
> > +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE	42
> > +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE	43
> > +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE	44
> > +#define IMX8ULP_CLK_SOSC_DIV1_GATE		45
> > +#define IMX8ULP_CLK_SOSC_DIV2_GATE		46
> > +#define IMX8ULP_CLK_SOSC_DIV3_GATE		47
> > +#define IMX8ULP_CLK_FROSC_DIV1_GATE		48
> > +#define IMX8ULP_CLK_FROSC_DIV2_GATE		49
> > +#define IMX8ULP_CLK_FROSC_DIV3_GATE		50
> > +#define IMX8ULP_CLK_SAI4_SEL			51
> > +#define IMX8ULP_CLK_SAI5_SEL			52
> > +#define IMX8ULP_CLK_AUD_CLK1			53
> > +#define IMX8ULP_CLK_ARM				54
> > +#define IMX8ULP_CLK_ENET_TS_SEL			55
> > +
> > +#define IMX8ULP_CLK_CGC1_END			56
> > +
> > +/* CGC2 */
> > +#define IMX8ULP_CLK_PLL4_PRE_SEL	0
> > +#define IMX8ULP_CLK_PLL4		1
> > +#define IMX8ULP_CLK_PLL4_VCODIV		2
> > +#define IMX8ULP_CLK_DDR_SEL		3
> > +#define IMX8ULP_CLK_DDR_DIV		4
> > +#define IMX8ULP_CLK_LPAV_AXI_SEL	5
> > +#define IMX8ULP_CLK_LPAV_AXI_DIV	6
> > +#define IMX8ULP_CLK_LPAV_AHB_DIV	7
> > +#define IMX8ULP_CLK_LPAV_BUS_DIV	8
> > +#define IMX8ULP_CLK_PLL4_PFD0		9
> > +#define IMX8ULP_CLK_PLL4_PFD1		10
> > +#define IMX8ULP_CLK_PLL4_PFD2		11
> > +#define IMX8ULP_CLK_PLL4_PFD3		12
> > +#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE	13
> > +#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE	14
> > +#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE	15
> > +#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE	16
> > +#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE	17
> > +#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE	18
> > +#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE	19
> > +#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE	20
> > +#define IMX8ULP_CLK_PLL4_PFD0_DIV1	21
> > +#define IMX8ULP_CLK_PLL4_PFD0_DIV2	22
> > +#define IMX8ULP_CLK_PLL4_PFD1_DIV1	23
> > +#define IMX8ULP_CLK_PLL4_PFD1_DIV2	24
> > +#define IMX8ULP_CLK_PLL4_PFD2_DIV1	25
> > +#define IMX8ULP_CLK_PLL4_PFD2_DIV2	26
> > +#define IMX8ULP_CLK_PLL4_PFD3_DIV1	27
> > +#define IMX8ULP_CLK_PLL4_PFD3_DIV2	28
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE	29
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE	30
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE	31
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV1	32
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV2	33
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV3	34
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE	35
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE	36
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE	37
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV1	38
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV2	39
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV3	40
> > +#define IMX8ULP_CLK_AUD_CLK2		41
> > +#define IMX8ULP_CLK_SAI6_SEL		42
> > +#define IMX8ULP_CLK_SAI7_SEL		43
> > +#define IMX8ULP_CLK_SPDIF_SEL		44
> > +#define IMX8ULP_CLK_HIFI_SEL		45
> > +#define IMX8ULP_CLK_HIFI_DIVCORE	46
> > +#define IMX8ULP_CLK_HIFI_DIVPLAT	47
> > +#define IMX8ULP_CLK_DSI_PHY_REF		48
> > +
> > +#define IMX8ULP_CLK_CGC2_END		49
> > +
> > +/* PCC3 */
> > +#define IMX8ULP_CLK_WDOG3		0
> > +#define IMX8ULP_CLK_WDOG4		1
> > +#define IMX8ULP_CLK_LPIT1		2
> > +#define IMX8ULP_CLK_TPM4		3
> > +#define IMX8ULP_CLK_TPM5		4
> > +#define IMX8ULP_CLK_FLEXIO1		5
> > +#define IMX8ULP_CLK_I3C2		6
> > +#define IMX8ULP_CLK_LPI2C4		7
> > +#define IMX8ULP_CLK_LPI2C5		8
> > +#define IMX8ULP_CLK_LPUART4		9
> > +#define IMX8ULP_CLK_LPUART5		10
> > +#define IMX8ULP_CLK_LPSPI4		11
> > +#define IMX8ULP_CLK_LPSPI5		12
> > +#define IMX8ULP_CLK_DMA1_MP		13
> > +#define IMX8ULP_CLK_DMA1_CH0		14
> > +#define IMX8ULP_CLK_DMA1_CH1		15
> > +#define IMX8ULP_CLK_DMA1_CH2		16
> > +#define IMX8ULP_CLK_DMA1_CH3		17
> > +#define IMX8ULP_CLK_DMA1_CH4		18
> > +#define IMX8ULP_CLK_DMA1_CH5		19
> > +#define IMX8ULP_CLK_DMA1_CH6		20
> > +#define IMX8ULP_CLK_DMA1_CH7		21
> > +#define IMX8ULP_CLK_DMA1_CH8		22
> > +#define IMX8ULP_CLK_DMA1_CH9		23
> > +#define IMX8ULP_CLK_DMA1_CH10		24
> > +#define IMX8ULP_CLK_DMA1_CH11		25
> > +#define IMX8ULP_CLK_DMA1_CH12		26
> > +#define IMX8ULP_CLK_DMA1_CH13		27
> > +#define IMX8ULP_CLK_DMA1_CH14		28
> > +#define IMX8ULP_CLK_DMA1_CH15		29
> > +#define IMX8ULP_CLK_DMA1_CH16		30
> > +#define IMX8ULP_CLK_DMA1_CH17		31
> > +#define IMX8ULP_CLK_DMA1_CH18		32
> > +#define IMX8ULP_CLK_DMA1_CH19		33
> > +#define IMX8ULP_CLK_DMA1_CH20		34
> > +#define IMX8ULP_CLK_DMA1_CH21		35
> > +#define IMX8ULP_CLK_DMA1_CH22		36
> > +#define IMX8ULP_CLK_DMA1_CH23		37
> > +#define IMX8ULP_CLK_DMA1_CH24		38
> > +#define IMX8ULP_CLK_DMA1_CH25		39
> > +#define IMX8ULP_CLK_DMA1_CH26		40
> > +#define IMX8ULP_CLK_DMA1_CH27		41
> > +#define IMX8ULP_CLK_DMA1_CH28		42
> > +#define IMX8ULP_CLK_DMA1_CH29		43
> > +#define IMX8ULP_CLK_DMA1_CH30		44
> > +#define IMX8ULP_CLK_DMA1_CH31		45
> > +#define IMX8ULP_CLK_MU3_A		46
> > +
> > +#define IMX8ULP_CLK_PCC3_END		47
> > +
> > +/* PCC4 */
> > +#define IMX8ULP_CLK_FLEXSPI2		0
> > +#define IMX8ULP_CLK_TPM6		1
> > +#define IMX8ULP_CLK_TPM7		2
> > +#define IMX8ULP_CLK_LPI2C6		3
> > +#define IMX8ULP_CLK_LPI2C7		4
> > +#define IMX8ULP_CLK_LPUART6		5
> > +#define IMX8ULP_CLK_LPUART7		6
> > +#define IMX8ULP_CLK_SAI4		7
> > +#define IMX8ULP_CLK_SAI5		8
> > +#define IMX8ULP_CLK_PCTLE		9
> > +#define IMX8ULP_CLK_PCTLF		10
> > +#define IMX8ULP_CLK_USDHC0		11
> > +#define IMX8ULP_CLK_USDHC1		12
> > +#define IMX8ULP_CLK_USDHC2		13
> > +#define IMX8ULP_CLK_USB0		14
> > +#define IMX8ULP_CLK_USB0_PHY		15
> > +#define IMX8ULP_CLK_USB1		16
> > +#define IMX8ULP_CLK_USB1_PHY		17
> > +#define IMX8ULP_CLK_USB_XBAR		18
> > +#define IMX8ULP_CLK_ENET		19
> > +#define IMX8ULP_CLK_SFA1		20
> > +#define IMX8ULP_CLK_RGPIOE		21
> > +#define IMX8ULP_CLK_RGPIOF		22
> > +
> > +#define IMX8ULP_CLK_PCC4_END		23
> > +
> > +/* PCC5 */
> > +#define IMX8ULP_CLK_TPM8		0
> > +#define IMX8ULP_CLK_SAI6		1
> > +#define IMX8ULP_CLK_SAI7		2
> > +#define IMX8ULP_CLK_SPDIF		3
> > +#define IMX8ULP_CLK_ISI			4
> > +#define IMX8ULP_CLK_CSI_REGS 		5
> > +#define IMX8ULP_CLK_PCTLD		6
> > +#define IMX8ULP_CLK_CSI			7
> > +#define IMX8ULP_CLK_DSI			8
> > +#define IMX8ULP_CLK_WDOG5		9
> > +#define IMX8ULP_CLK_EPDC		10
> > +#define IMX8ULP_CLK_PXP			11
> > +#define IMX8ULP_CLK_SFA2		12
> > +#define IMX8ULP_CLK_GPU2D		13
> > +#define IMX8ULP_CLK_GPU3D		14
> > +#define IMX8ULP_CLK_DC_NANO		15
> > +#define IMX8ULP_CLK_CSI_CLK_UI 		16
> > +#define IMX8ULP_CLK_CSI_CLK_ESC		17
> > +#define IMX8ULP_CLK_RGPIOD		18
> > +#define IMX8ULP_CLK_DMA2_MP		19
> > +#define IMX8ULP_CLK_DMA2_CH0		20
> > +#define IMX8ULP_CLK_DMA2_CH1		21
> > +#define IMX8ULP_CLK_DMA2_CH2		22
> > +#define IMX8ULP_CLK_DMA2_CH3		23
> > +#define IMX8ULP_CLK_DMA2_CH4		24
> > +#define IMX8ULP_CLK_DMA2_CH5		25
> > +#define IMX8ULP_CLK_DMA2_CH6		26
> > +#define IMX8ULP_CLK_DMA2_CH7		27
> > +#define IMX8ULP_CLK_DMA2_CH8		28
> > +#define IMX8ULP_CLK_DMA2_CH9		29
> > +#define IMX8ULP_CLK_DMA2_CH10		30
> > +#define IMX8ULP_CLK_DMA2_CH11		31
> > +#define IMX8ULP_CLK_DMA2_CH12		32
> > +#define IMX8ULP_CLK_DMA2_CH13		33
> > +#define IMX8ULP_CLK_DMA2_CH14		34
> > +#define IMX8ULP_CLK_DMA2_CH15		35
> > +#define IMX8ULP_CLK_DMA2_CH16		36
> > +#define IMX8ULP_CLK_DMA2_CH17		37
> > +#define IMX8ULP_CLK_DMA2_CH18		38
> > +#define IMX8ULP_CLK_DMA2_CH19		39
> > +#define IMX8ULP_CLK_DMA2_CH20		40
> > +#define IMX8ULP_CLK_DMA2_CH21		41
> > +#define IMX8ULP_CLK_DMA2_CH22		42
> > +#define IMX8ULP_CLK_DMA2_CH23		43
> > +#define IMX8ULP_CLK_DMA2_CH24		44
> > +#define IMX8ULP_CLK_DMA2_CH25		45
> > +#define IMX8ULP_CLK_DMA2_CH26		46
> > +#define IMX8ULP_CLK_DMA2_CH27		47
> > +#define IMX8ULP_CLK_DMA2_CH28		48
> > +#define IMX8ULP_CLK_DMA2_CH29		49
> > +#define IMX8ULP_CLK_DMA2_CH30		50
> > +#define IMX8ULP_CLK_DMA2_CH31		51
> > +#define IMX8ULP_CLK_MU2_B		52
> > +#define IMX8ULP_CLK_MU3_B		53
> > +#define IMX8ULP_CLK_AVD_SIM		54
> > +#define IMX8ULP_CLK_DSI_TX_ESC		55
> > +
> > +#define IMX8ULP_CLK_PCC5_END		56
> > +
> > +#endif
> > --
> > 2.26.2
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^ permalink raw reply	[flat|nested] 36+ messages in thread

* RE: [PATCH 10/11] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp
  2021-06-17  9:03     ` Jacky Bai
@ 2021-06-18  1:41       ` Jacky Bai
  0 siblings, 0 replies; 36+ messages in thread
From: Jacky Bai @ 2021-06-18  1:41 UTC (permalink / raw)
  To: Rob Herring
  Cc: shawnguo, sboyd, s.hauer, linus.walleij, Aisheng Dong, festevam,
	kernel, dl-linux-imx, devicetree, linux-arm-kernel

> Subject: RE: [PATCH 10/11] arm64: dts: imx8ulp: Add the basic dtsi file for
> imx8ulp
> 
> > Subject: Re: [PATCH 10/11] arm64: dts: imx8ulp: Add the basic dtsi
> > file for imx8ulp
> >
> > On Mon, Jun 07, 2021 at 04:39:20PM +0800, Jacky Bai wrote:
> > > Add the basic dtsi support for i.MX8ULP.
> > >
> > > i.MX 8ULP is part of the ULP family with emphasis on extreme
> > > low-power techniques using the 28 nm fully depleted silicon on
> > > insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be based
> > > on asymmetric architecture, however will add a third DSP domain for
> > > advanced voice/audio capability and a Graphics domain where it is
> > > possible to access graphics resources from the application side or
> > > the realtime side.
> > >
> > > Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> > > ---
> > >  .../boot/dts/freescale/imx8ulp-pinfunc.h      | 978
> > ++++++++++++++++++
> > >  arch/arm64/boot/dts/freescale/imx8ulp.dtsi    | 474 +++++++++
> > >  2 files changed, 1452 insertions(+)  create mode 100755
> > > arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> > >  create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> > > b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> > > new file mode 100755
> > > index 000000000000..faa702634a38
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> > > @@ -0,0 +1,978 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> >
> >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > > new file mode 100644
> > > index 000000000000..469c2dcd4636
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > > @@ -0,0 +1,474 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >
> > How can I use MIT when GPL only header is included? Dual license the
> > header please.
> >
> 
> Ok, will add Dual license in the above file.
> 
> > And NXP is good with GPLv3, GPLv4, etc.?
> 
> It seems no file use GPLv3 in latest kernel, I will keep use GPLv2 for now, is it
> ok?

Sorry, Rob, it seems I misunderstand what you mean ^_^. I just checked the NXP license policy, GPLv2 or later is ok.

BR
Jacky Bai
> 
> BR
> Jacky Bai
> >
> > > +/*
> > > + * Copyright 2021 NXP
> > > + */
> > > +
> > > +#include <dt-bindings/clock/imx8ulp-clock.h>
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +
> > > +#include "imx8ulp-pinfunc.h"
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^ permalink raw reply	[flat|nested] 36+ messages in thread

end of thread, other threads:[~2021-06-18  1:43 UTC | newest]

Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-07  8:39 [PATCH 00/11] Add imx8ulp basic dtsi support Jacky Bai
2021-06-07  8:39 ` [PATCH 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
2021-06-09 10:56   ` Linus Walleij
2021-06-11 13:45   ` Dong Aisheng
2021-06-16 23:42   ` Rob Herring
2021-06-07  8:39 ` [PATCH 02/11] dt-bindings: i2c: imx-lpi2c: " Jacky Bai
2021-06-11 13:46   ` Dong Aisheng
2021-06-16 23:43   ` Rob Herring
2021-06-07  8:39 ` [PATCH 03/11] dt-bindings: mmc: imx-esdhc: Add imx8ulp compatibe string Jacky Bai
2021-06-11 13:50   ` Dong Aisheng
2021-06-16 23:44   ` Rob Herring
2021-06-07  8:39 ` [PATCH 04/11] dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string Jacky Bai
2021-06-11 13:52   ` Dong Aisheng
2021-06-16 23:44   ` Rob Herring
2021-06-07  8:39 ` [PATCH 05/11] dt-bindings: spi: fsl-lpspi: " Jacky Bai
2021-06-11 13:57   ` Dong Aisheng
2021-06-16 23:45   ` Rob Herring
2021-06-07  8:39 ` [PATCH 06/11] dt-bindings: timer: tpm-timer: " Jacky Bai
2021-06-11 13:58   ` Dong Aisheng
2021-06-16 23:45   ` Rob Herring
2021-06-07  8:39 ` [PATCH 07/11] dt-bindings: watchdog: imx7ulp-wdt: " Jacky Bai
2021-06-11 13:58   ` Dong Aisheng
2021-06-16 23:45   ` Rob Herring
2021-06-07  8:39 ` [PATCH 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk Jacky Bai
2021-06-11 13:59   ` Dong Aisheng
2021-06-16 23:46   ` Rob Herring
2021-06-07  8:39 ` [PATCH 09/11] dt-bindings: clock: Add imx8ulp clock support Jacky Bai
2021-06-11 14:17   ` Dong Aisheng
2021-06-16 23:47   ` Rob Herring
2021-06-17  9:09     ` Jacky Bai
2021-06-07  8:39 ` [PATCH 11/11] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board Jacky Bai
2021-06-11 14:43   ` Dong Aisheng
     [not found] ` <20210607083921.2668568-11-ping.bai@nxp.com>
2021-06-11 14:40   ` [PATCH 10/11] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp Aisheng Dong
2021-06-16 23:51   ` Rob Herring
2021-06-17  9:03     ` Jacky Bai
2021-06-18  1:41       ` Jacky Bai

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