From: Alim Akhtar <alim.akhtar@samsung.com>
To: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org
Cc: krzysztof.kozlowski@canonical.com,
linux-samsung-soc@vger.kernel.org,
Alim Akhtar <alim.akhtar@samsung.com>
Subject: [PATCH v2 1/2] arm64: dts: exynos7: Add cpu cache information
Date: Tue, 22 Jun 2021 18:35:50 +0530 [thread overview]
Message-ID: <20210622130551.67446-1-alim.akhtar@samsung.com> (raw)
In-Reply-To: CGME20210622130203epcas5p48a3111fc6586b1bfe0bd3cb90f783ce0@epcas5p4.samsung.com
This patch adds cpu caches information to its dt
nodes so that the same is available to userspace
via sysfs.
This SoC has 48/32 KB I/D cache for each cores
and 2MB of L2 cache.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
Changes since v1:
* no change in this patch
* changes as per Krzysztof's review comments in patch 2/2
arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 10244e59d56d..8b06397ba6e7 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -54,6 +54,13 @@
compatible = "arm,cortex-a57";
reg = <0x0>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu_atlas1: cpu@1 {
@@ -61,6 +68,13 @@
compatible = "arm,cortex-a57";
reg = <0x1>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu_atlas2: cpu@2 {
@@ -68,6 +82,13 @@
compatible = "arm,cortex-a57";
reg = <0x2>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu_atlas3: cpu@3 {
@@ -75,6 +96,20 @@
compatible = "arm,cortex-a57";
reg = <0x3>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
+ };
+
+ atlas_l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
};
};
base-commit: 614124bea77e452aa6df7a8714e8bc820b489922
--
2.17.1
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next parent reply other threads:[~2021-06-22 13:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20210622130203epcas5p48a3111fc6586b1bfe0bd3cb90f783ce0@epcas5p4.samsung.com>
2021-06-22 13:05 ` Alim Akhtar [this message]
[not found] ` <CGME20210622130204epcas5p1192cd38abc4a0b49798355cecea9f763@epcas5p1.samsung.com>
2021-06-22 13:05 ` [PATCH v2 2/2] arm64: dts: exynos5433: Add cpu cache information Alim Akhtar
2021-06-23 6:08 ` [PATCH v2 1/2] arm64: dts: exynos7: " Krzysztof Kozlowski
2021-07-15 18:46 ` Krzysztof Kozlowski
2021-07-15 18:47 ` Krzysztof Kozlowski
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