From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 877A0C07E95 for ; Wed, 7 Jul 2021 12:57:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5153561CB9 for ; Wed, 7 Jul 2021 12:57:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5153561CB9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=f+aRqvHMkc1d4R3hDDy+BSiN98a/jVQxWR9fpNz5+cM=; b=XXJoGQbZOIIRiW Xlt1saZ9Ak4avCpyaeLo8rj450V7P90BZmRluFeVpAjfm7ZLG4GW4yMq9ZswZFQMVsniAbm2ieZlY 2dVXiUDq7bKHLrn3F9Q9B6qxLoRL/G30lthnhsMtDmMQkomquYlbwvEOCZZUOsO6COCJ4MNzGGQr5 t4X8tRskx3JHAxEJ0nb04B4qgxF3SjVU0mKpYMpXsZJ1MyWiYutF6TNAaw4DHVOz/joADfOYnOP0y JCz8B0Erzzg7UHgjHiEV7vHtX+aniykk1Y5aYqz4i/h/Fk7ALasEkSlFO8DmuS7n+N3MzEhwI8NAA 2R/QH6dCwuk/Tp/WGpFQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m175l-00Epzb-Ea; Wed, 07 Jul 2021 12:55:53 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m175h-00Epyu-K6 for linux-arm-kernel@lists.infradead.org; Wed, 07 Jul 2021 12:55:51 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 214A561CB9; Wed, 7 Jul 2021 12:55:47 +0000 (UTC) Date: Wed, 7 Jul 2021 13:55:45 +0100 From: Catalin Marinas To: Will Deacon Cc: Peter Collingbourne , Szabolcs Nagy , Vincenzo Frascino , Evgenii Stepanov , Linux ARM , Tejas Belagod Subject: Re: [PATCH v5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Message-ID: <20210707125544.GB24397@arm.com> References: <20210625120137.GC20835@arm.com> <20210625123959.GB3170@willie-the-truck> <20210625135350.GD20835@arm.com> <20210628101448.GA5503@willie-the-truck> <20210628152023.GA9308@arm.com> <20210629104625.GA7168@willie-the-truck> <20210630151906.GD3426@arm.com> <20210707103003.GA21767@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210707103003.GA21767@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210707_055549_751708_35A33668 X-CRM114-Status: GOOD ( 48.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jul 07, 2021 at 11:30:04AM +0100, Will Deacon wrote: > On Wed, Jun 30, 2021 at 04:39:02PM -0700, Peter Collingbourne wrote: > > On Wed, Jun 30, 2021 at 8:19 AM Catalin Marinas wrote: > > > On Tue, Jun 29, 2021 at 12:11:17PM -0700, Peter Collingbourne wrote: > > > > On Tue, Jun 29, 2021 at 3:46 AM Will Deacon wrote: > > > > > On Mon, Jun 28, 2021 at 04:20:24PM +0100, Catalin Marinas wrote: > > > > > > Another option is a mapping table where async can be remapped to sync > > > > > > and sync to async (or even to "none" for both). That's not far from one > > > > > > of Peter's mte-upgrade-async proposal, we just add mte-map-async and > > > > > > mte-map-sync options. Most likely we'll just use mte-map-async for now > > > > > > to map it to sync on some CPUs but it wouldn't exclude other forced > > > > > > settings. > > > > > > > > > > Catalin and I discussed this offline and ended up with another option: > > > > > retrospectively change the prctl() ABI so that the 'flags' argument > > > > > accepts a bitmask of modes that the application is willing to accept. This > > > > > doesn't break any existing users, as we currently enforce that only one > > > > > mode is specified, but it would allow things like: > > > > > > > > > > prctl(PR_SET_TAGGED_ADDR_CTRL, > > > > > PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC, > > > > > 0, 0, 0); > > > > > > > > > > which is actually very similar to Peter's PR_MTE_DYNAMIC_TCF proposal, with > > > > > the difference that I think this extends more naturally as new PR_MTR_TCF_* > > > > > flags are introduced. > > > > > > > > > > Then we expose a per-cpu file in sysfs (say "cpuX/mte_tcf_preferred") > > > > > which initially reads as "async". If the root user does, e.g. > > > > > > > > > > # echo "sync" > cpu1/mte_tcf_preferred > > > > > > > > > > then a task which has successfully issued a PR_SET_TAGGED_ADDR_CTRL prctl() > > > > > request for PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC will run in sync mode on > > > > > CPU1, but async mode on other CPUs (assuming they retain the default value). > > > > > > > > > > We'll need to special-case PR_MTE_TCF_NONE, as that's just a shorthand for > > > > > "no flags" so doing PR_MTE_TCF_NONE | PR_MTE_TCF_SYNC is just the same as > > > > > doing PR_MTE_TCF_SYNC (which I think is already the behaviour today). The > > > > > only values which the sysfs files would accept today are "sync" and "async". > > > > > > > > > > When faced with a situation where the prctl() flags for a task do not > > > > > intersect with the preferred mode for a CPU on which the task is going > > > > > to run, the lowest bit number flag is chosen from the mask set by the > > > > > prctl(). > > > > > > > > > > Thoughts? > > > > > > > > This all sounds great and I'm glad you were able to come to an > > > > agreement on this. I'll get started on implementing it. > > > > > > > > Once we have ASYM support I'm not sure if we can rely on bit numbering > > > > for ordering, as we will want the ordering to be ASYNC < ASYM < SYNC > > > > and ASYNC is bit-adjacent to SYNC. So I think we will need to make > > > > ASYM a special case. > > > > > > The bit position based order - SYNC < ASYNC < ASYM - is indeed arbitrary > > > but I think it's easier to follow. When we add ASYM, it will be the last > > > one rather than squeezing it in the middle of the current order. Any > > > other order somehow implies that one is better than the other but we > > > don't have a clear definition for "better". > > > > At least from my perspective "more strict" is a reasonable enough > > definition for "better", at least by default, since it seems like what > > most users would want. If users really want a different ordering, > > perhaps it can be an opt-in behavior. > > I think some of this hinges on how we want to handle something like a > request for PR_MTE_TCF_ASYM | PR_MTE_TCF_ASYNC on a system which doesn't > have hardware support for PR_MTE_TCF_ASYM. If this returns an error from > the prctl(), then I'm not strongly opposed to having a "more strict" > priority ordering for the options, but if this was to succeed, then I think > we need something like the bit-position ordering so that the user-visible > behaviour doesn't change in a non-discoverable manner based on what the CPU > supports. I replied on a subsequent update to this series and I think leaving it as imp def is best ;) (as with other ARM architecture behaviours). https://lore.kernel.org/r/20210701170450.GC12484@arm.com -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel