From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7469CC07E95 for ; Tue, 13 Jul 2021 18:15:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 40CC461152 for ; Tue, 13 Jul 2021 18:15:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 40CC461152 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=F1h1kUqXIMGqUff5fcGROV/OerptfsdMm+0BpAg5v/c=; b=eYggLV2V7X/Dkq 94t5vyUTMLFLcY9d7bfu1WuesCpoSWwVylffsfaJB8sO01zWPReDLv7uoapQEkeXsUXTRLBPl6Gkh UpWMomlWfVjwtMktEWqMqcDrIpcsJHC++zk4oHobD+kanz1UCi44SSkMswWSmksWxMX+OyJ/PIHRt H+RUFd1dWGs98t1CV5yDkjXWU46FDh+XLx0983X2ZAjmPJMpXuKwYmRUd/BFszkekYcowJqPyEj1O 85N9XLmtEGUTMP68WDPbiEXPuyxhBJNhvGFj5JkX96Gg4fLvPP7ahRkJuyjtyMwLV0wCuStRop5x2 ihVhr2FapDZxO+zUwr9w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3MuD-00B8OF-WF; Tue, 13 Jul 2021 18:13:18 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3Mu9-00B8NI-Ni for linux-arm-kernel@lists.infradead.org; Tue, 13 Jul 2021 18:13:15 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 16A2361374; Tue, 13 Jul 2021 18:13:09 +0000 (UTC) Date: Tue, 13 Jul 2021 19:13:02 +0100 From: Catalin Marinas To: "Russell King (Oracle)" Cc: Leo Yan , Will Deacon , Arnaldo Carvalho de Melo , Adrian Hunter , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Thomas Gleixner , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" , Mathieu Poirier , Suzuki K Poulose , Mike Leach , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 11/11] perf auxtrace: Add compat_auxtrace_mmap__{read_head|write_tail} Message-ID: <20210713181301.GE13181@arm.com> References: <20210711104105.505728-1-leo.yan@linaro.org> <20210711104105.505728-12-leo.yan@linaro.org> <20210712144410.GE22278@shell.armlinux.org.uk> <20210713154602.GD748506@leoy-ThinkPad-X240s> <20210713161441.GK22278@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210713161441.GK22278@shell.armlinux.org.uk> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_111313_847943_6BF5FA80 X-CRM114-Status: GOOD ( 36.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 13, 2021 at 05:14:41PM +0100, Russell King wrote: > On Tue, Jul 13, 2021 at 11:46:02PM +0800, Leo Yan wrote: > > On Mon, Jul 12, 2021 at 03:44:11PM +0100, Russell King (Oracle) wrote: > > > On Sun, Jul 11, 2021 at 06:41:05PM +0800, Leo Yan wrote: > > > > When perf runs in compat mode (kernel in 64-bit mode and the perf is in > > > > 32-bit mode), the 64-bit value atomicity in the user space cannot be > > > > assured, E.g. on some architectures, the 64-bit value accessing is split > > > > into two instructions, one is for the low 32-bit word accessing and > > > > another is for the high 32-bit word. > > > > > > Does this apply to 32-bit ARM code on aarch64? I would not have thought > > > it would, as the structure member is a __u64 and > > > compat_auxtrace_mmap__read_head() doesn't seem to be marking anything > > > as packed, so the compiler _should_ be able to use a LDRD instruction > > > to load the value. > > > > I think essentially your question is relevant to the memory model. > > For 32-bit Arm application on aarch64, in the Armv8 architecture > > reference manual ARM DDI 0487F.c, chapter "E2.2.1 > > Requirements for single-copy atomicity" describes: > > > > "LDM, LDC, LDRD, STM, STC, STRD, PUSH, POP, RFE, SRS, VLDM, VLDR, VSTM, > > and VSTR instructions are executed as a sequence of word-aligned word > > accesses. Each 32-bit word access is guaranteed to be single-copy > > atomic. The architecture does not require subsequences of two or more > > word accesses from the sequence to be single-copy atomic." > > ... which is an interesting statement for ARMv7 code. DDI0406C says > similar but goes on to say: > > In an implementation that includes the Large Physical Address > Extension, LDRD and STRD accesses to 64-bit aligned locations > are 64-bit single-copy atomic as seen by translation table > walks and accesses to translation tables. > > then states that LPAE page tables must be stored in memory that such > page tables must be in memory that is capable of supporting 64-bit > single-copy atomic accesses. A similar statement is in the ARMv8 ARM (E2.2.1 in version G.a). > In Linux, we assume all RAM that the kernel has access to can contain > page tables. So by implication, all RAM that the kernel has access to > and exposes to userspace must be 64-bit single-copy atomic (if not, > we have a rather serious bug.) Indeed. We should assume that the SDRAM supports all the CPU features. > The remaining question is whether it would be sane for LDRD and STRD > to be single-copy atomic to translation table walkers but not to other > CPUs. Since Linux expects to be able to modify the page tables from > any CPU in the system, this requirement must hold, otherwise it's going > to be a really strangely designed system. The above statement does say "translation table walks and accesses to translation tables". The accesses can be LDRD/STRD instructions from other CPUs. Since the hardware can't tell whether the access is to a page table, the designers just made LDRD/STRD single-copy atomic. > I'd be interested to hear what Catalin and Will have to say on this, > but I suspect in practice, Arm systems that are running Linux with > LPAE (ARMv7+LPAE, ARMv8) will implement LDRD and STRD with 64-bit > single-copy atomic semantics. That's my understanding as well. In theory one could have a page table access from EL0, so it should be atomic. We could try to clarify E2.2.1 to simply state that naturally aligned LDRD/STRD are single-copy atomic without any subsequent statement on the translation table. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel