From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06771C12002 for ; Wed, 21 Jul 2021 07:20:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CEB6360BD3 for ; Wed, 21 Jul 2021 07:20:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CEB6360BD3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Tj+pgK3T9YINNl6AdwgdQNMV8Y37Olx3MsHvsszy6+A=; b=zDYuxLHg7gd/6x Z6xIXraWhG5Cuj8Ulfh+s5fVIfMsrn3UTKCbICBxPsmfA5KoI6DFG2CIY90y7oUOQfnbVreTG5/cX 7a/sFHdQZ+FwHWbdf+WMj3b+QuXmefZFupOGWItUaQoTZy9nREgLMrV1GM63TzsDvi3jda7kjz9rT c1PmYgSgVPH5jwRfwvk3HfgiaNUarXkNTJ+XVgHcxYu4rBVBRVkS3ppHYUMoxVS58oNXjXSSYAqpT p/WosJ3w42yyIqRYGVPillq9ZeNDBOxZcW2mqBtGL65Q+OuzxE6MOCoyeeU2Np/Kez6LA6mlD6fMq YH4zyLP4nDYY7XkVR9fw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m66Vl-00EeC6-6b; Wed, 21 Jul 2021 07:19:21 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m66VH-00Ee3I-K3; Wed, 21 Jul 2021 07:18:53 +0000 X-UUID: e6a007cc9fad4a05b68df3619d67202a-20210721 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=G2AmQ6oMotefYATogTQxUTlM3BiwW47YMnXr26U0/n4=; b=iqx5wNxVJbFLoTQmn8yqna5JXFA2JjvOBn84sYpS0jWXahgkbE4dMSEmg+SeRleUKGg1XAbrnSdabl8Z5wmNwnJxpywFwLQu/fc9nU44gz0W7I2fW89Av6dTcXGod2/uOSVdQEV9HO6okpNOidYs3uls2QqOXZo1zev9IG5UBMQ=; X-UUID: e6a007cc9fad4a05b68df3619d67202a-20210721 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1492372075; Wed, 21 Jul 2021 00:18:47 -0700 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 21 Jul 2021 00:09:08 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 21 Jul 2021 15:09:05 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 21 Jul 2021 15:09:05 +0800 From: Roger Lu To: Matthias Brugger , Enric Balletbo Serra , Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd , Philipp Zabel CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Nishanth Menon , Roger Lu , , , , , , , Guenter Roeck Subject: [PATCH v20 4/7] soc: mediatek: SVS: add debug commands Date: Wed, 21 Jul 2021 15:09:01 +0800 Message-ID: <20210721070904.15636-5-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210721070904.15636-1-roger.lu@mediatek.com> References: <20210721070904.15636-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210721_001851_740580_5ACD3072 X-CRM114-Status: GOOD ( 20.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The purpose of SVS is to help find the suitable voltages for DVFS. Therefore, if SVS bank voltages are concerned to be wrong, we can adjust SVS bank voltages by this patch. Signed-off-by: Roger Lu --- drivers/soc/mediatek/mtk-svs.c | 328 +++++++++++++++++++++++++++++++++ 1 file changed, 328 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 013667752ec2..ad2a184e4471 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -62,6 +64,39 @@ #define SVSB_INTSTS_COMPLETE 0x1 #define SVSB_INTSTS_CLEAN 0x00ffffff +#define debug_fops_ro(name) \ + static int svs_##name##_debug_open(struct inode *inode, \ + struct file *filp) \ + { \ + return single_open(filp, svs_##name##_debug_show, \ + inode->i_private); \ + } \ + static const struct file_operations svs_##name##_debug_fops = { \ + .owner = THIS_MODULE, \ + .open = svs_##name##_debug_open, \ + .read = seq_read, \ + .llseek = seq_lseek, \ + .release = single_release, \ + } + +#define debug_fops_rw(name) \ + static int svs_##name##_debug_open(struct inode *inode, \ + struct file *filp) \ + { \ + return single_open(filp, svs_##name##_debug_show, \ + inode->i_private); \ + } \ + static const struct file_operations svs_##name##_debug_fops = { \ + .owner = THIS_MODULE, \ + .open = svs_##name##_debug_open, \ + .read = seq_read, \ + .write = svs_##name##_debug_write, \ + .llseek = seq_lseek, \ + .release = single_release, \ + } + +#define svs_dentry(name) {__stringify(name), &svs_##name##_debug_fops} + static DEFINE_SPINLOCK(mtk_svs_lock); /* @@ -83,6 +118,7 @@ enum svsb_phase { SVSB_PHASE_INIT01, SVSB_PHASE_INIT02, SVSB_PHASE_MON, + SVSB_PHASE_NUM, }; enum svs_reg_index { @@ -140,6 +176,7 @@ enum svs_reg_index { SPARE2, SPARE3, THSLPEVEB, + SVS_REG_NUM, }; static const u32 svs_regs_v2[] = { @@ -284,6 +321,7 @@ struct svs_platform { * @opp_volts: signed-off voltages from default opp table * @freqs_pct: percent of "opp_freqs / freq_base" for bank init * @volts: bank voltages + * @reg_data: bank register data of each phase * @freq_base: reference frequency for bank init * @vboot: voltage request for bank init01 stage only * @volt_step: bank voltage step @@ -302,6 +340,7 @@ struct svs_platform { * @opp_count: bank opp count * @int_st: bank interrupt identification * @sw_id: bank software identification + * @hw_id: bank hardware identification * @ctl0: bank thermal sensor selection * @cpu_id: cpu core id for SVS CPU only * @@ -330,6 +369,7 @@ struct svs_bank { u32 opp_volts[16]; u32 freqs_pct[16]; u32 volts[16]; + u32 reg_data[SVSB_PHASE_NUM][SVS_REG_NUM]; u32 freq_base; u32 vboot; u32 volt_step; @@ -367,6 +407,7 @@ struct svs_bank { u32 opp_count; u32 int_st; u32 sw_id; + u32 hw_id; u32 ctl0; u32 cpu_id; }; @@ -648,11 +689,15 @@ static void svs_set_bank_phase(struct svs_platform *svsp, static inline void svs_init01_isr_handler(struct svs_platform *svsp) { struct svs_bank *svsb = svsp->pbank; + enum svs_reg_index rg_i; dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", __func__, svs_readl(svsp, VDESIGN74), svs_readl(svsp, VDESIGN30), svs_readl(svsp, DCVALUES)); + for (rg_i = DESCHAR; rg_i < SVS_REG_NUM; rg_i++) + svsb->reg_data[SVSB_PHASE_INIT01][rg_i] = svs_readl(svsp, rg_i); + svsb->phase = SVSB_PHASE_INIT01; svsb->dc_voffset_in = ~(svs_readl(svsp, DCVALUES) & GENMASK(15, 0)) + 1; if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || @@ -672,11 +717,15 @@ static inline void svs_init01_isr_handler(struct svs_platform *svsp) static inline void svs_init02_isr_handler(struct svs_platform *svsp) { struct svs_bank *svsb = svsp->pbank; + enum svs_reg_index rg_i; dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", __func__, svs_readl(svsp, VOP74), svs_readl(svsp, VOP30), svs_readl(svsp, DCVALUES)); + for (rg_i = DESCHAR; rg_i < SVS_REG_NUM; rg_i++) + svsb->reg_data[SVSB_PHASE_INIT02][rg_i] = svs_readl(svsp, rg_i); + svsb->phase = SVSB_PHASE_INIT02; svsb->get_vops(svsp); @@ -687,6 +736,10 @@ static inline void svs_init02_isr_handler(struct svs_platform *svsp) static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp) { struct svs_bank *svsb = svsp->pbank; + enum svs_reg_index rg_i; + + for (rg_i = DESCHAR; rg_i < SVS_REG_NUM; rg_i++) + svsb->reg_data[SVSB_PHASE_MON][rg_i] = svs_readl(svsp, rg_i); svsb->phase = SVSB_PHASE_MON; svsb->temp = svs_readl(svsp, TEMP) & GENMASK(7, 0); @@ -698,6 +751,7 @@ static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp) static inline void svs_error_isr_handler(struct svs_platform *svsp) { struct svs_bank *svsb = svsp->pbank; + enum svs_reg_index rg_i; dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", __func__, svs_readl(svsp, CORESEL)); @@ -707,6 +761,9 @@ static inline void svs_error_isr_handler(struct svs_platform *svsp) svs_readl(svsp, SMSTATE0), svs_readl(svsp, SMSTATE1)); dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl(svsp, TEMP)); + for (rg_i = DESCHAR; rg_i < SVS_REG_NUM; rg_i++) + svsb->reg_data[SVSB_PHASE_ERROR][rg_i] = svs_readl(svsp, rg_i); + svsb->mode_support = SVSB_MODE_ALL_DISABLE; svsb->phase = SVSB_PHASE_ERROR; @@ -1412,11 +1469,273 @@ static int svs_resume(struct device *dev) return 0; } +/* + * svs_dump_debug_show - dump svs/thermal efuse and svs banks' registers + */ +static int svs_dump_debug_show(struct seq_file *m, void *p) +{ + struct svs_platform *svsp = (struct svs_platform *)m->private; + struct svs_bank *svsb; + unsigned long svs_reg_addr; + u32 idx, i, j; + + for (i = 0; i < svsp->efuse_num; i++) + if (svsp->efuse && svsp->efuse[i]) + seq_printf(m, "M_HW_RES%d = 0x%08x\n", + i, svsp->efuse[i]); + + for (i = 0; i < svsp->tefuse_num; i++) + if (svsp->tefuse) + seq_printf(m, "THERMAL_EFUSE%d = 0x%08x\n", + i, svsp->tefuse[i]); + + for (idx = 0; idx < svsp->bank_num; idx++) { + svsb = &svsp->banks[idx]; + + for (i = SVSB_PHASE_INIT01; i <= SVSB_PHASE_MON; i++) { + seq_printf(m, "Bank_number = %u\n", svsb->hw_id); + + if (i == SVSB_PHASE_INIT01 || i == SVSB_PHASE_INIT02) + seq_printf(m, "mode = init%d\n", i); + else if (i == SVSB_PHASE_MON) + seq_puts(m, "mode = mon\n"); + else + seq_puts(m, "mode = error\n"); + + for (j = DESCHAR; j < SVS_REG_NUM; j++) { + svs_reg_addr = (unsigned long)(svsp->base + + svsp->regs[j]); + seq_printf(m, "0x%08lx = 0x%08x\n", + svs_reg_addr, svsb->reg_data[i][j]); + } + } + } + + return 0; +} + +debug_fops_ro(dump); + +/* + * svs_enable_debug_show - show svs bank current enable phase + */ +static int svs_enable_debug_show(struct seq_file *m, void *v) +{ + struct svs_bank *svsb = (struct svs_bank *)m->private; + + if (svsb->phase == SVSB_PHASE_INIT01) + seq_puts(m, "init1\n"); + else if (svsb->phase == SVSB_PHASE_INIT02) + seq_puts(m, "init2\n"); + else if (svsb->phase == SVSB_PHASE_MON) + seq_puts(m, "mon mode\n"); + else if (svsb->phase == SVSB_PHASE_ERROR) + seq_puts(m, "disabled\n"); + else + seq_puts(m, "unknown\n"); + + return 0; +} + +/* + * svs_enable_debug_write - we only support svs bank disable control + */ +static ssize_t svs_enable_debug_write(struct file *filp, + const char __user *buffer, + size_t count, loff_t *pos) +{ + struct svs_bank *svsb = file_inode(filp)->i_private; + struct svs_platform *svsp = dev_get_drvdata(svsb->dev); + unsigned long flags; + int enabled, ret; + char *buf = NULL; + + if (count >= PAGE_SIZE) + return -EINVAL; + + buf = (char *)memdup_user_nul(buffer, count); + if (IS_ERR(buf)) + return PTR_ERR(buf); + + ret = kstrtoint(buf, 10, &enabled); + if (ret) + return ret; + + if (!enabled) { + spin_lock_irqsave(&mtk_svs_lock, flags); + svsp->pbank = svsb; + svsb->mode_support = SVSB_MODE_ALL_DISABLE; + svs_switch_bank(svsp); + svs_writel(svsp, SVSB_EN_OFF, SVSEN); + svs_writel(svsp, SVSB_INTSTS_CLEAN, INTSTS); + spin_unlock_irqrestore(&mtk_svs_lock, flags); + + svsb->phase = SVSB_PHASE_ERROR; + svs_adjust_pm_opp_volts(svsb, true); + } + + kfree(buf); + + return count; +} + +debug_fops_rw(enable); + +/* + * svs_status_debug_show - show svs bank's tzone_temp/voltages/freqs_pct + * and its corresponding opp-table's opp_freqs/opp_volts + */ +static int svs_status_debug_show(struct seq_file *m, void *v) +{ + struct svs_bank *svsb = (struct svs_bank *)m->private; + struct dev_pm_opp *opp; + int tzone_temp = 0, ret; + u32 i; + + ret = svs_get_bank_zone_temperature(svsb->tzone_name, &tzone_temp); + if (ret) + seq_printf(m, "%s: no \"%s\" zone?\n", svsb->name, + svsb->tzone_name); + else + seq_printf(m, "%s: temperature = %d\n", svsb->name, tzone_temp); + + for (i = 0; i < svsb->opp_count; i++) { + opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, + svsb->opp_freqs[i], true); + if (IS_ERR(opp)) { + seq_printf(m, "%s: cannot find freq = %u (%ld)\n", + svsb->name, svsb->opp_freqs[i], + PTR_ERR(opp)); + return PTR_ERR(opp); + } + + seq_printf(m, "opp_freqs[%02u]: %u, opp_volts[%02u]: %lu, ", + i, svsb->opp_freqs[i], i, + dev_pm_opp_get_voltage(opp)); + seq_printf(m, "svsb_volts[%02u]: 0x%x, freqs_pct[%02u]: %u\n", + i, svsb->volts[i], i, svsb->freqs_pct[i]); + dev_pm_opp_put(opp); + } + + return 0; +} + +debug_fops_ro(status); + +/* + * svs_volt_offset_debug_show - show svs bank's voltage offset + */ +static int svs_volt_offset_debug_show(struct seq_file *m, void *v) +{ + struct svs_bank *svsb = (struct svs_bank *)m->private; + + seq_printf(m, "%d\n", svsb->volt_offset); + + return 0; +} + +/* + * svs_volt_offset_debug_write - write svs bank's voltage offset + */ +static ssize_t svs_volt_offset_debug_write(struct file *filp, + const char __user *buffer, + size_t count, loff_t *pos) +{ + struct svs_bank *svsb = file_inode(filp)->i_private; + char *buf = NULL; + s32 volt_offset; + + if (count >= PAGE_SIZE) + return -EINVAL; + + buf = (char *)memdup_user_nul(buffer, count); + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (!kstrtoint(buf, 10, &volt_offset)) { + svsb->volt_offset = volt_offset; + svs_adjust_pm_opp_volts(svsb, true); + } + + kfree(buf); + + return count; +} + +debug_fops_rw(volt_offset); + +static int svs_create_svs_debug_cmds(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct dentry *svs_dir, *svsb_dir, *file_entry; + const char *d = "/sys/kernel/debug/svs"; + u32 i, idx; + + struct svs_dentry { + const char *name; + const struct file_operations *fops; + }; + + struct svs_dentry svs_entries[] = { + svs_dentry(dump), + }; + + struct svs_dentry svsb_entries[] = { + svs_dentry(enable), + svs_dentry(status), + svs_dentry(volt_offset), + }; + + svs_dir = debugfs_create_dir("svs", NULL); + if (IS_ERR(svs_dir)) { + dev_err(svsp->dev, "cannot create %s: %ld\n", + d, PTR_ERR(svs_dir)); + return 0; + } + + for (i = 0; i < ARRAY_SIZE(svs_entries); i++) { + file_entry = debugfs_create_file(svs_entries[i].name, 0664, + svs_dir, svsp, + svs_entries[i].fops); + if (IS_ERR(file_entry)) { + dev_err(svsp->dev, "cannot create %s/%s: %ld\n", + d, svs_entries[i].name, PTR_ERR(file_entry)); + return PTR_ERR(file_entry); + } + } + + for (idx = 0; idx < svsp->bank_num; idx++) { + svsb = &svsp->banks[idx]; + + svsb_dir = debugfs_create_dir(svsb->name, svs_dir); + if (IS_ERR(svsb_dir)) { + dev_err(svsp->dev, "cannot create %s/%s: %ld\n", + d, svsb->name, PTR_ERR(svsb_dir)); + return PTR_ERR(svsb_dir); + } + + for (i = 0; i < ARRAY_SIZE(svsb_entries); i++) { + file_entry = debugfs_create_file(svsb_entries[i].name, + 0664, svsb_dir, svsb, + svsb_entries[i].fops); + if (IS_ERR(file_entry)) { + dev_err(svsp->dev, "no %s/%s/%s?: %ld\n", + d, svsb->name, svsb_entries[i].name, + PTR_ERR(file_entry)); + return PTR_ERR(file_entry); + } + } + } + + return 0; +} + static struct svs_bank svs_mt8183_banks[] = { { .sw_id = SVSB_CPU_LITTLE, .set_freqs_pct = svs_set_freqs_pct_v2, .get_vops = svs_get_vops_v2, + .hw_id = 0, .cpu_id = 0, .tzone_name = "tzts4", .buck_name = "proc", @@ -1454,6 +1773,7 @@ static struct svs_bank svs_mt8183_banks[] = { .sw_id = SVSB_CPU_BIG, .set_freqs_pct = svs_set_freqs_pct_v2, .get_vops = svs_get_vops_v2, + .hw_id = 1, .cpu_id = 4, .tzone_name = "tzts5", .buck_name = "proc", @@ -1491,6 +1811,7 @@ static struct svs_bank svs_mt8183_banks[] = { .sw_id = SVSB_CCI, .set_freqs_pct = svs_set_freqs_pct_v2, .get_vops = svs_get_vops_v2, + .hw_id = 2, .tzone_name = "tzts4", .buck_name = "proc", .pd_req = false, @@ -1527,6 +1848,7 @@ static struct svs_bank svs_mt8183_banks[] = { .sw_id = SVSB_GPU, .set_freqs_pct = svs_set_freqs_pct_v2, .get_vops = svs_get_vops_v2, + .hw_id = 3, .tzone_name = "tzts2", .buck_name = "mali", .pd_req = true, @@ -1691,6 +2013,12 @@ static int svs_probe(struct platform_device *pdev) goto svs_probe_iounmap; } + ret = svs_create_svs_debug_cmds(svsp); + if (ret) { + dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); + goto svs_probe_iounmap; + } + return 0; svs_probe_iounmap: -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel