From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42BA5C4320A for ; Thu, 29 Jul 2021 13:58:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 10C7960FED for ; Thu, 29 Jul 2021 13:58:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 10C7960FED Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZXJZHWDJOwvswvj8nPrWof//UVIw3el28NtNtNcfyQA=; b=46PRZAb6tin25j KqS2JjpjbgWkmjDNn/VhCcTGwk9vIW2dFBtO/x91bTjRpD2/NSW1B6qhI8jwlh87y2YgO7KOeY74i a42/cDnlLlJUR5QpPFh9qrmroEPHmb3ZmWAoZBW2XepmtjnsNK+SuUizLo2G9qY6959mMH4WoHXrW mYXy244mcQaoe8O+oFQZLyflEU8u87JkjrlH/V9iiD8at9AXdgqtDCJ4GWbp/Swj74WTyNC9VWJOL 0ehTq7SgFmLaB3DdTQsghLiC6NLrZsaVg45lRnJ7s+gejSLTMV20lgfV16zUBjXUvTKCa/m3m6T0E yaDVz+bo6B+7aWH06qKg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m96WV-004OUP-2l; Thu, 29 Jul 2021 13:56:31 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m96WO-004OST-7l for linux-arm-kernel@lists.infradead.org; Thu, 29 Jul 2021 13:56:26 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 57D9B6D; Thu, 29 Jul 2021 06:56:21 -0700 (PDT) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8B4A43F70D; Thu, 29 Jul 2021 06:56:20 -0700 (PDT) Date: Thu, 29 Jul 2021 14:54:59 +0100 From: Dave Martin To: Sebastian Andrzej Siewior Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Thomas Gleixner Subject: Re: [PATCH] arm64/sve: Make kernel FPU protection RT friendly Message-ID: <20210729135459.GL1724@arm.com> References: <20210729105215.2222338-1-bigeasy@linutronix.de> <20210729105215.2222338-3-bigeasy@linutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210729105215.2222338-3-bigeasy@linutronix.de> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210729_065624_396647_3A5A66DD X-CRM114-Status: GOOD ( 19.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 29, 2021 at 12:52:15PM +0200, Sebastian Andrzej Siewior wrote: > Non RT kernels need to protect FPU against preemption and bottom half > processing. This is achieved by disabling bottom halves via > local_bh_disable() which implictly disables preemption. > > On RT kernels this protection mechanism is not sufficient because > local_bh_disable() does not disable preemption. It serializes bottom half > related processing via a CPU local lock. > > As bottom halves are running always in thread context on RT kernels > disabling preemption is the proper choice as it implicitly prevents bottom > half processing. > > Signed-off-by: Sebastian Andrzej Siewior > --- > arch/arm64/kernel/fpsimd.c | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c > index e098f6c67b1de..a208514bd69a9 100644 > --- a/arch/arm64/kernel/fpsimd.c > +++ b/arch/arm64/kernel/fpsimd.c > @@ -177,10 +177,19 @@ static void __get_cpu_fpsimd_context(void) > * > * The double-underscore version must only be called if you know the task > * can't be preempted. > + * > + * On RT kernels local_bh_disable() is not sufficient because it only > + * serializes soft interrupt related sections via a local lock, but stays > + * preemptible. Disabling preemption is the right choice here as bottom > + * half processing is always in thread context on RT kernels so it > + * implicitly prevents bottom half processing as well. > */ > static void get_cpu_fpsimd_context(void) > { > - local_bh_disable(); > + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) > + local_bh_disable(); > + else > + preempt_disable(); Is this wrongly abstracted for RT? The requirement here is that the code should temporarily be nonpreemptible by anything except hardirq context. Having to do this conditional everywhere that is required feels fragile. Is a similar thing needed anywhere else? If bh (as a preempting context) doesn't exist on RT, then can't local_bh_disable() just suppress all preemption up to but excluding hardirq? Would anything break? [...] Cheers ---Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel