From: Yong Wu <yong.wu@mediatek.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
"Tomasz Figa" <tfiga@chromium.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>, <yong.wu@mediatek.com>,
<youlin.pei@mediatek.com>, <anan.sun@mediatek.com>,
<ming-fan.chen@mediatek.com>, <yi.kuo@mediatek.com>,
<anthony.huang@mediatek.com>, Ikjoon Jang <ikjn@chromium.org>
Subject: [PATCH v3 11/13] memory: mtk-smi: mt8195: Add initial setting for smi-common
Date: Tue, 10 Aug 2021 16:08:57 +0800 [thread overview]
Message-ID: <20210810080859.29511-12-yong.wu@mediatek.com> (raw)
In-Reply-To: <20210810080859.29511-1-yong.wu@mediatek.com>
To improve the performance, add initial setting for smi-common.
some register use some fix setting(suggested from DE).
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 42 ++++++++++++++++++++++++++++++++++++----
1 file changed, 38 insertions(+), 4 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 35853ba980c9..689a45b39a65 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -18,11 +18,19 @@
#include <dt-bindings/memory/mtk-memory-port.h>
/* SMI COMMON */
+#define SMI_L1LEN 0x100
+
#define SMI_BUS_SEL 0x220
#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
/* All are MMU0 defaultly. Only specialize mmu1 here. */
#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
+#define SMI_M4U_TH 0x234
+#define SMI_FIFO_TH1 0x238
+#define SMI_FIFO_TH2 0x23c
+#define SMI_DCM 0x300
+#define SMI_DUMMY 0x444
+
/* SMI LARB */
/* Below are about mmu enable registers, they are different in SoCs */
@@ -59,6 +67,13 @@
(_id << 8 | _id << 10 | _id << 12 | _id << 14); \
})
+#define SMI_COMMON_INIT_REGS_NR 6
+
+struct mtk_smi_reg_pair {
+ unsigned int offset;
+ u32 value;
+};
+
enum mtk_smi_type {
MTK_SMI_GEN1,
MTK_SMI_GEN2, /* gen2 smi common */
@@ -85,6 +100,8 @@ struct mtk_smi_common_plat {
enum mtk_smi_type type;
bool has_gals;
u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
+
+ const struct mtk_smi_reg_pair *init;
};
struct mtk_smi_larb_gen {
@@ -419,6 +436,15 @@ static struct platform_driver mtk_smi_larb_driver = {
}
};
+static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
+ {SMI_L1LEN, 0xb},
+ {SMI_M4U_TH, 0xe100e10},
+ {SMI_FIFO_TH1, 0x506090a},
+ {SMI_FIFO_TH2, 0x506090a},
+ {SMI_DCM, 0x4f1},
+ {SMI_DUMMY, 0x1},
+};
+
static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
.type = MTK_SMI_GEN1,
};
@@ -453,12 +479,14 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
.has_gals = true,
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
F_MMU1_LARB(7),
+ .init = mtk_smi_common_mt8195_init,
};
static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
.type = MTK_SMI_GEN2,
.has_gals = true,
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
+ .init = mtk_smi_common_mt8195_init,
};
static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
@@ -551,15 +579,21 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
static int __maybe_unused mtk_smi_common_resume(struct device *dev)
{
struct mtk_smi *common = dev_get_drvdata(dev);
- u32 bus_sel = common->plat->bus_sel;
- int ret;
+ const struct mtk_smi_reg_pair *init = common->plat->init;
+ u32 bus_sel = common->plat->bus_sel; /* default is 0 */
+ int ret, i;
ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
if (ret)
return ret;
- if (common->plat->type == MTK_SMI_GEN2 && bus_sel)
- writel(bus_sel, common->base + SMI_BUS_SEL);
+ if (common->plat->type != MTK_SMI_GEN2)
+ return 0;
+
+ for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
+ writel_relaxed(init[i].value, common->base + init[i].offset);
+
+ writel(bus_sel, common->base + SMI_BUS_SEL);
return 0;
}
--
2.18.0
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next prev parent reply other threads:[~2021-08-10 8:23 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-10 8:08 [PATCH v3 00/13] MT8195 SMI support Yong Wu
2021-08-10 8:08 ` [PATCH v3 01/13] dt-bindings: memory: mediatek: Add mt8195 smi binding Yong Wu
2021-08-10 8:08 ` [PATCH v3 02/13] dt-bindings: memory: mediatek: Add mt8195 smi sub common Yong Wu
2021-08-17 20:12 ` Rob Herring
2021-08-10 8:08 ` [PATCH v3 03/13] memory: mtk-smi: Use clk_bulk clock ops Yong Wu
2021-08-10 8:08 ` [PATCH v3 04/13] memory: mtk-smi: Rename smi_gen to smi_type Yong Wu
2021-08-10 8:08 ` [PATCH v3 05/13] memory: mtk-smi: Adjust some code position Yong Wu
2021-08-10 8:08 ` [PATCH v3 06/13] memory: mtk-smi: Add error handle for smi_probe Yong Wu
2021-08-10 8:08 ` [PATCH v3 07/13] memory: mtk-smi: Add device link for smi-sub-common Yong Wu
2021-08-10 8:08 ` [PATCH v3 08/13] memory: mtk-smi: Add clocks " Yong Wu
2021-08-10 8:08 ` [PATCH v3 09/13] memory: mtk-smi: Use devm_platform_ioremap_resource Yong Wu
2021-08-10 8:08 ` [PATCH v3 10/13] memory: mtk-smi: mt8195: Add smi support Yong Wu
2021-08-10 8:08 ` Yong Wu [this message]
2021-08-10 8:08 ` [PATCH v3 12/13] memory: mtk-smi: mt8195: Add initial setting for smi-larb Yong Wu
2021-08-10 8:08 ` [PATCH v3 13/13] MAINTAINERS: Add entry for MediaTek SMI Yong Wu
2021-08-18 20:41 ` [PATCH v3 00/13] MT8195 SMI support Krzysztof Kozlowski
2021-08-19 5:34 ` Yong Wu (吴勇)
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