From: Will Deacon <will@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, "Rafał Miłecki" <zajec5@gmail.com>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Mark Rutland" <mark.rutland@arm.com>,
"Ard Biesheuvel" <ardb@kernel.org>,
"Florian Fainelli" <f.fainelli@gmail.com>,
bcm-kernel-feedback-list@broadcom.com, kernel-team@android.com
Subject: Re: [PATCH 3/5] arm64: Detect disabled HVC early
Date: Fri, 13 Aug 2021 10:05:40 +0100 [thread overview]
Message-ID: <20210813090539.GA7536@willie-the-truck> (raw)
In-Reply-To: <20210812190213.2601506-4-maz@kernel.org>
On Thu, Aug 12, 2021 at 08:02:11PM +0100, Marc Zyngier wrote:
> Having HVC disabled from EL3 while the kernel is entered at EL2
> is a complete nightmare.
>
> We end-up taking an UNDEF at the worse possible moment (checking
> for VHE) and even if we didn't, having KVM enabled would signify
> the premature end of the kernel.
>
> Instead, try and detect this stupid case by issuing a HVC
> for HVC_RESET_VECTORS, which does nothing when the stubs
> are live. If we get HVC_STUB_ERR back, that's because the
> UNDEF handler has kicked in.
>
> In this situation, close your eyes, block your nose, and gracefully
> pretend we have booted at EL1.
>
> Reported-by: Rafał Miłecki <zajec5@gmail.com>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/kernel/head.S | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> index 9d5aa56a98cc..d6b2b05f5d3a 100644
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -519,6 +519,28 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
> msr vbar_el2, x0
> isb
>
> + // Check that HVC actually works...
> + mov x0, #HVC_RESET_VECTORS
> + hvc #0
> +
> + mov_q x1, HVC_STUB_ERR
> + cmp x0, x1
> + b.ne 0f
> +
> + /*
> + * HVC is unusable, so pretend we actually booted at EL1.
> + * Once we have left EL2, there will be no going back.
> + */
This comment got me thinking...
.macro host_hvc0
mrs xzr, actlr_el1
.endm
then set HCR_EL2.TACR=1 while we still can and match the ISS against a
constant in the handler. Too awful?
Will
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next prev parent reply other threads:[~2021-08-13 9:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-12 19:02 [PATCH 0/5] arm64: Survival kit for SCR_EL3.HCE==0 conditions Marc Zyngier
2021-08-12 19:02 ` [PATCH 1/5] arm64: Directly expand __init_el2_nvhe_prepare_eret where needed Marc Zyngier
2021-08-12 19:02 ` [PATCH 2/5] arm64: Handle UNDEF in the EL2 stub vectors Marc Zyngier
2021-08-13 13:08 ` Robin Murphy
2021-08-13 17:41 ` Marc Zyngier
2021-08-13 18:17 ` Robin Murphy
2021-08-14 9:38 ` Marc Zyngier
2021-08-12 19:02 ` [PATCH 3/5] arm64: Detect disabled HVC early Marc Zyngier
2021-08-12 19:47 ` Rafał Miłecki
2021-08-13 9:05 ` Will Deacon [this message]
2021-08-13 17:33 ` Marc Zyngier
2021-08-12 19:02 ` [PATCH 4/5] arm64: Warn on booting at EL2 with HVC disabled Marc Zyngier
2021-08-12 19:58 ` Rafał Miłecki
2021-08-12 19:02 ` [PATCH 5/5] arm64: Document the requirement for SCR_EL3.HCE Marc Zyngier
2021-08-24 10:49 ` Catalin Marinas
2021-08-24 10:52 ` Mark Rutland
2021-08-15 7:28 ` [PATCH 0/5] arm64: Survival kit for SCR_EL3.HCE==0 conditions Florian Fainelli
2021-08-15 9:27 ` Marc Zyngier
2021-08-22 11:31 ` Florian Fainelli
2021-08-24 16:19 ` (subset) " Catalin Marinas
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