On Tue, Aug 24, 2021 at 04:45:23PM +0100, Alexandru Elisei wrote: > Commit 31c00d2aeaa2 ("arm64: Disable fine grained traps on boot") zeroed > the fine grained trap registers to prevent unwanted register traps from > occuring. However, for the PMSNEVFR_EL1 register, the corresponding > HDFG{R,W}TR_EL2.nPMSNEVFR_EL1 fields must be 1 to disable trapping. Set > both fields to 1 if FEAT_SPEv1p2 is detected to disable read and write > traps. Reviewed-by: Mark Brown