From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E53AC433FE for ; Mon, 11 Oct 2021 11:04:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0443A60EB4 for ; Mon, 11 Oct 2021 11:04:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0443A60EB4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=71U9XwywqcX+c13gD5X+PlLP1jQSCADJs5EmTv3j35Q=; b=IKxqi68G0oW2t9 llNV2FPIRl4Wd0qB/ogyjd0dD5XT/rFCBLMl+pqkuWKIefBuvJWVUdv9n6AWvOmpB1vFEPEv0lxi1 e7EiPeSaPplGg5W6csTUukzi27yKcaN94by6xMZh0/NO2sObR1NqDmxlkDn/si9s1sT5RU50KATk1 9wkgTA+/erAQBrERl4CxXc3XE/RPRfrSc2TtjscB7y/NiW3UV/vafluSHNonW5sKnN0MXdILsSRCA HxiPRbbVyATYG+d5SGuSN5utNWp73ckTk8Z8ueD5j+r1K0ZHnL/8bATooOBSARkGfVFyL1/ioSnyN CFRlUETmVUGJxKrGeKUg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mZt53-008yTV-HQ; Mon, 11 Oct 2021 11:02:53 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mZt4z-008ySG-U0 for linux-arm-kernel@lists.infradead.org; Mon, 11 Oct 2021 11:02:51 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7B41460EB1; Mon, 11 Oct 2021 11:02:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1633950169; bh=Oi1WJOMEIm5nh0AAd4dmHC8O35/60euaedtnJCwMV7s=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=W/WGpwMN9duErrEx9Z7StzfvIWALhqdOvDhkFkspt04zOct5qTvWSHRCTc5R1/KN+ B8TgFUUPbnYFb5Jbjim7tlk/Y4P0Cow2udEufTl2h1YItt1cD04icaeHkI0VXrsvit Z5dIi9wrTlE/QKOTDw9cBlA5YEOJGY82ONlFqPBJWnKtWzulivDOgN47z9G//tM73l aIxRGfGzbfnNS6AA1Ceu79ljfvWUY+sSsswMfzFHbw8gtN8DKct9QARKk1TMFQc3TN 2T2/XSBYOOxVKjBxCViLpJO7kkxjWMvQu5jFq3UEoKPQMOuVVGJUkthbXV8/M/JNso Rt5zdq5YCvHjw== Date: Mon, 11 Oct 2021 12:02:44 +0100 From: Will Deacon To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Rutland , Daniel Lezcano , Thomas Gleixner , Peter Shier , Raghavendra Rao Ananta , Ricardo Koller , Oliver Upton , Catalin Marinas , Linus Walleij , kernel-team@android.com Subject: Re: [PATCH v3 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support Message-ID: <20211011110243.GB4068@willie-the-truck> References: <20211010114306.2910453-1-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211010114306.2910453-1-maz@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211011_040250_007129_B20C4328 X-CRM114-Status: GOOD ( 21.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Oct 10, 2021 at 12:42:49PM +0100, Marc Zyngier wrote: > This is v3 of the series enabling ARMv8.6 support for timer subsystem, > and was prompted by a discussion with Oliver around the fact that an > ARMv8.6 implementation must have a 1GHz counter, which leads to a > number of things to break in the timer code: > > - the counter rollover can come pretty quickly as we only advertise a > 56bit counter, > - the maximum timer delta can be remarkably small, as we use the > countdown interface which is limited to 32bit... > > Thankfully, there is a way out: we can compute the minimal width of > the counter based on the guarantees that the architecture gives us, > and we can use the 64bit comparator interface instead of the countdown > to program the timer. > > Finally, we start making use of the ARMv8.6 ECV features by switching > accesses to the counters to a self-synchronising register, removing > the need for an ISB. Hopefully, implementations will *not* just stick > an invisible ISB there... > > A side effect of the switch to CVAL is that XGene-1 breaks. I have > added a workaround to keep it alive. > > I have added Oliver's original patch[0] to the series and tweaked a > couple of things. Blame me if I broke anything. > > The whole things has been tested on Juno (sysreg + MMIO timers), > XGene-1 (broken sysreg timers), FVP (FEAT_ECV, CNT*CTSS_EL0). The arm64 bits look pretty good to me (I left some minor comments). How do you want to merge this series? It would be nice to have the arch bits in the arm64 tree, if possible, as we'll be tripping over the cpucaps stuff otherwise. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel