From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0D59C433EF for ; Mon, 11 Oct 2021 17:00:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BFF9C60FD7 for ; Mon, 11 Oct 2021 17:00:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BFF9C60FD7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=marcan.st Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BmeOJsIjIW9xLRRcDzImpZKtbuWUOgrXDfebKtIk8ZE=; b=bgzNluYjAjENs9 PMXwiGXfpaC9zZVZyVK8xuP6Y2T6Qn7n1ndntgeVvIv03vbO0U0FWp/gNtmcbGk9PLAShGrHjl+/p yrq1Z1fpbWKd6BeJqSDMPRwHrO11z2gAfOeMdLCQl3k5cmhOPrIaSdPfLHglXPQO0TpvXJRziyo5c HJD1dqpTMVYMG2v3ggLQRHM9sLanjNtw1D2jQ9fQcKDE759Yo4mP6vYmR8D5NWBz2i0duThTK8+iq twDczRD4Ey+OmC76/AgvCropc+CcPgqfSQjb0G7HhiFuZN+lEbox5AzFRdigtR0KQJKwWZ/fZ31q0 QPiAln4fwTLd9AcDj0mA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mZycu-00A8O2-FR; Mon, 11 Oct 2021 16:58:12 +0000 Received: from marcansoft.com ([212.63.210.85] helo=mail.marcansoft.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mZycV-00A8H0-Ll for linux-arm-kernel@lists.infradead.org; Mon, 11 Oct 2021 16:57:49 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: hector@marcansoft.com) by mail.marcansoft.com (Postfix) with ESMTPSA id F3A2042462; Mon, 11 Oct 2021 16:57:40 +0000 (UTC) From: Hector Martin To: linux-arm-kernel@lists.infradead.org Cc: Hector Martin , Alyssa Rosenzweig , Sven Peter , Marc Zyngier , Mark Kettenis , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Viresh Kumar , Nishanth Menon , Catalin Marinas , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 3/9] dt-bindings: clock: Add apple,cluster-clk binding Date: Tue, 12 Oct 2021 01:57:01 +0900 Message-Id: <20211011165707.138157-4-marcan@marcan.st> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211011165707.138157-1-marcan@marcan.st> References: <20211011165707.138157-1-marcan@marcan.st> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211011_095747_888623_3A75B733 X-CRM114-Status: GOOD ( 18.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This device represents the CPU performance state switching mechanism as a clock controller, to be used with the standard cpufreq-dt infrastructure. Signed-off-by: Hector Martin --- .../bindings/clock/apple,cluster-clk.yaml | 115 ++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/apple,cluster-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/apple,cluster-clk.yaml b/Documentation/devicetree/bindings/clock/apple,cluster-clk.yaml new file mode 100644 index 000000000000..9a8b863dadc0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/apple,cluster-clk.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/apple,cluster-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CPU cluster frequency scaling for Apple SoCs + +maintainers: + - Hector Martin + +description: | + Apple SoCs control CPU cluster frequencies by using a performance state + index. This node represents the feature as a clock controller, and uses + a reference to the CPU OPP table to translate clock frequencies into + performance states. This allows the CPUs to use the standard cpufreq-dt + mechanism for frequency scaling. + +properties: + compatible: + items: + - enum: + - apple,t8103-cluster-clk + - const: apple,cluster-clk + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + operating-points-v2: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A reference to the OPP table used for the CPU cluster controlled by this + device instance. The table should contain an `opp-level` property for + every OPP, which represents the p-state index used by the hardware to + represent this performance level. + + OPPs may also have a `required-opps` property (see power-domains). + + power-domains: + maxItems: 1 + description: + An optional reference to a power domain provider that links its + performance state to the CPU cluster performance state. This is typically + a memory controller. If set, the `required-opps` property in the CPU + frequency OPP nodes will be used to change the performance state of this + provider state in tandem with CPU frequency changes. + +required: + - compatible + - reg + - '#clock-cells' + - operating-points-v2 + +additionalProperties: false + + +examples: + - | + pcluster_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <781000>; + opp-level = <1>; + clock-latency-ns = <8000>; + required-opps = <&mcc_lowperf>; + }; + /* intermediate p-states omitted */ + opp15 { + opp-hz = /bits/ 64 <3204000000>; + opp-microvolt = <1081000>; + opp-level = <15>; + clock-latency-ns = <56000>; + required-opps = <&mcc_highperf>; + }; + }; + + mcc_opp: opp-table-2 { + compatible = "operating-points-v2"; + + mcc_lowperf: opp0 { + opp-level = <0>; + apple,memory-perf-config = <0x813057f 0x1800180>; + }; + mcc_highperf: opp1 { + opp-level = <1>; + apple,memory-perf-config = <0x133 0x55555340>; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + + mcc: memory-controller@200200000 { + compatible = "apple,t8103-mcc", "apple,mcc"; + #power-domain-cells = <0>; + reg = <0x2 0x200000 0x0 0x200000>; + operating-points-v2 = <&mcc_opp>; + apple,num-channels = <8>; + }; + + clk_pcluster: clock-controller@211e20000 { + compatible = "apple,t8103-cluster-clk", "apple,cluster-clk"; + #clock-cells = <0>; + reg = <0x2 0x11e20000 0x0 0x4000>; + operating-points-v2 = <&pcluster_opp>; + power-domains = <&mcc>; + }; + }; -- 2.33.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel