From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH 3/3] ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce
Date: Wed, 20 Oct 2021 12:46:56 +0300 [thread overview]
Message-ID: <20211020094656.3343242-4-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20211020094656.3343242-1-claudiu.beznea@microchip.com>
Use blocks 0 and 1 of TCB0 for clocksource and clockevent functionality.
PIT64B is already enabled on SAMA7G5 targets for this but TCB0 will be
used as a fallback only in case PIT64B will fail to probe.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/at91-sama7g5ek.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
index 0f53b2db28a2..0e1975c6812e 100644
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
@@ -687,6 +687,18 @@ &spdiftx {
status = "okay";
};
+&tcb0 {
+ timer0: timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
&trng {
status = "okay";
};
--
2.25.1
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next prev parent reply other threads:[~2021-10-20 9:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-20 9:46 [PATCH 0/3] ARM: dts: at91: enable leftover IPs Claudiu Beznea
2021-10-20 9:46 ` [PATCH 1/3] ARM: dts: at91: sama7g5: add rtc node Claudiu Beznea
2021-10-20 9:46 ` [PATCH 2/3] ARM: dts: at91: sama7g5: add tcb nodes Claudiu Beznea
2021-10-20 9:46 ` Claudiu Beznea [this message]
2021-10-21 11:47 ` [PATCH 0/3] ARM: dts: at91: enable leftover IPs Nicolas Ferre
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