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From: Martin Kepplinger <martin.kepplinger@puri.sm>
To: shawnguo@kernel.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com
Cc: peng.fan@nxp.com, l.stach@pengutronix.de, kernel@puri.sm,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Martin Kepplinger <martin.kepplinger@puri.sm>
Subject: [PATCH] soc: imx: gpcv2: avoid unbalanced powering off during system suspend
Date: Mon, 22 Nov 2021 12:51:45 +0100	[thread overview]
Message-ID: <20211122115145.177196-1-martin.kepplinger@puri.sm> (raw)

Yes, I don't yet sign-off on this - I'm not sure whether this works around
a probem in the power domain (or regulator?) core:

When tranisioning to system sleep on imx8mq I see the following errors
(and resuming doesn't succeed):

[ 2594.505465] ldo5: Underflow of regulator enable count
[ 2594.524045] imx-pgc imx-pgc-domain.0: failed to disable regulator: -22
[ 2594.531352] imx-pgc imx-pgc-domain.5: failed to disable regulator: -5
[ 2594.547119] imx-pgc imx-pgc-domain.6: failed to disable regulator: -5

So I started debugging the "ldo5" regulator that is the power-supply for
the imx8mq mipi power domain "0" (on the imx8mq-librem5 board).

During runtime-pm only, things are fine. When transitioning to system
suspend, I at least see genpd_power_off() executing after the
"System suspend is in progress" check, where it's supposed to have returned
early already (due to genpd->prepared_count > 0). That leads to the
unbalance power-off.

While this patch "fixes" my problem, where is the root cause of this?
Thank you for your help in this!

so long,
                                martin
---
 drivers/soc/imx/gpcv2.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index b8d52d8d29db..4b1b9176127f 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -318,6 +318,9 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 	u32 reg_val, pgc;
 	int ret;
 
+	if (pm_runtime_suspended(domain->dev))
+		return 0;
+
 	/* Enable reset clocks for all devices in the domain */
 	if (!domain->keep_clocks) {
 		ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
-- 
2.30.2


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                 reply	other threads:[~2021-11-22 12:15 UTC|newest]

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