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Mon, 22 Nov 2021 22:20:53 -0800 From: Tanmay Shah To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Michal Simek CC: Laurent Pinchart , Ben Levinsky , Bill Mills , Sergei Korneichuk , Tanmay Shah , , , , Subject: [PATCH v2 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Date: Mon, 22 Nov 2021 22:20:45 -0800 Message-ID: <20211123062050.1442712-2-tanmay.shah@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211123062050.1442712-1-tanmay.shah@xilinx.com> References: <20211123062050.1442712-1-tanmay.shah@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 305bf327-5b19-4af3-db35-08d9ae4967b0 X-MS-TrafficTypeDiagnostic: CH0PR02MB8259: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Y74LvEE0vzA3Rw3UNrhsWVyJ7yRvIUmuIygiyQ5RELrL+/H2JUMrrZ6he0D0LE9a0dywumNERrxpPVQtIfuhGWBPVrIY8uuZKLYzMQmSAOyjP/5itgrHUX+b4qQE9dvYrZ8YolHbZzwdgGBECe3SuhMDPzUIgTfXpOkjJFWgmVgsow7NaYtr5qb0FvKIxstRcwf0w812/xnfOGHftoTZp/LWMQaaXzlt1skVJ0P1UjBIa62YdX3s984/VgmqwxYhDLnWUp51HWptas6sKlx7pBO1GZF3NgGubhRmAi8tfD009Bnsqi8sSWCwkZiyKS//wA787abXe309bcY/VTuJt+Y9USqEqiaciYKbM9tQVBCY52MoxknKq2TBo5ogSkkPXGPQaqX9DlDbBm79YU719jdK8sQf5mzUyjIAnhksmsEoymvpdu282Pb5TQuQYeYCo+2gdXzzypuWoiKIvb/4ouoix30oanqknbWygytbZOva2fgJGtVt+h2mK0OdeZ1oDlg9P5Rw0326dCF+kcyCaUV0pFTv0YogWtrmITMtHf2pt0+PqVSS42W7K3YqZVBr8Gt0s64iPSISWrk7516tDv8CtXAk0UjqZyd3GMP0uNKEjiGmjKAc8r0hNIMQj+XzaPzXdZpj6/68hYF2VL2CG5HPRqjFIDs+inyXI5MajQSL8twHi1MqHdA51LH7QFsrVuEhRcPMznpuEjxUc8zeC5Q/RH6E3dumNc8hTWuVGkUEVQ7Kb6aiqQe3BSqC+pZKVJnwW1ldaJMDDUm3V88QFl+z5F70D8qSVCBsBIV6aUEKDoa6KUcLnvbs+82tMLXEC0ZvFVWKpJjg7F3UMgyjQtZyqEMo6ZO8JwnFMjeEShg= X-Forefront-Antispam-Report: CIP:149.199.62.198; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem (cluster). Signed-off-by: Tanmay Shah --- .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 139 ++++++++++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + 2 files changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml new file mode 100644 index 000000000000..d43f0b16ad7f --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx R5F processor subsystem + +maintainers: + - Ben Levinsky + - Tanmay Shah + +description: | + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for + real-time processing based on the Cortex-R5F processor core from ARM. + The Cortex-R5F processor implements the Arm v7-R architecture and includes a + floating-point unit that implements the Arm VFPv3 instruction set. + +properties: + compatible: + const: xlnx,zynqmp-r5fss + + xlnx,cluster-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The RPU MPCore can operate in split mode(Dual-processor performance), Safety + lock-step mode(Both RPU cores execute the same code in lock-step, + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while + core 1 runs normally). The processor does not support dynamic configuration. + Switching between modes is only permitted immediately after a processor reset. + If set to 1 then lockstep mode and if 0 then split mode. + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + reg: + items: + - description: RPU subsystem status and control registers + +patternProperties: + "^r5f-[a-f0-9]+$": + type: object + description: | + The RPU is located in the Low Power Domain of the Processor Subsystem. + Each processor includes separate L1 instruction and data caches and + tightly coupled memories (TCM). System memory is cacheable, but the TCM + memory space is non-cacheable. + + Each RPU contains one 64KB memory and two 32KB memories that + are accessed via the TCM A and B port interfaces, for a total of 128KB + per processor. In lock-step mode, the processor has access to 256KB of + TCM memory. + + properties: + compatible: + const: xlnx,zynqmp-r5f + + power-domains: + description: | + phandle to a PM domain provider node and an args specifier containing + the r5f0 and r5f1 node id value. + + reg: + items: + - description: RPU0 and RPU1 control and status registers + + mboxes: + items: + - description: | + Bi-directional channel to send data to RPU and receive ack from RPU. + Request and response message buffers are available and each buffer is 32 bytes. + - description: | + Bi-directional channel to receive data from RPU and send ack from RPU. + Request and response message buffers are available and each buffer is 32 bytes. + minItems: 1 + + mbox-names: + items: + - const: tx + - const: rx + minItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + description: | + phandles to one or more reserved on-chip SRAM regions. Other than TCM, + the RPU can execute instructions and access data from, the OCM memory, + the main DDR memory, and other system memories. + + The regions should be defined as child nodes of the respective SRAM + node, and should be defined as per the generic bindings in, + Documentation/devicetree/bindings/sram/sram.yaml + + memory-region: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandles to the reserved memory regions associated with the + remoteproc device. This is variable and describes the memories shared with + the remote processor (e.g. remoteproc firmware and carveouts, rpmsg + vrings, ...). This reserved memory region will be allocated on DDR memory. + See Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + + required: + - compatible + - power-domains + + unevaluatedProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + r5fss: r5fss@ff9a0000 { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + #address-cells = <1>; + #size-cells = <1>; + reg = <0xff9a0000 0x228>; + + r5f-0 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware 0x7>; + }; + + r5f-1 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware 0x8>; + }; + }; +... diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h index 0d9a412fd5e0..618024cbb20d 100644 --- a/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -6,6 +6,12 @@ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H +#define PD_RPU_0 7 +#define PD_RPU_1 8 +#define PD_R5_0_ATCM 15 +#define PD_R5_0_BTCM 16 +#define PD_R5_1_ATCM 17 +#define PD_R5_1_BTCM 18 #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel