From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
To: Rob Herring <robh+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de>
Cc: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 2/3] arm64: dts: rockchip: Add spi nodes on rk356x
Date: Sat, 27 Nov 2021 15:19:08 +0100 [thread overview]
Message-ID: <20211127141910.12649-3-frattaroli.nicolas@gmail.com> (raw)
In-Reply-To: <20211127141910.12649-1-frattaroli.nicolas@gmail.com>
This adds the four spi nodes (spi0, spi1, spi2, spi3) to the
rk356x dtsi. These are from the downstream device tree, though
I have double-checked that their interrupts and DMA numbers are
correct. I have also tested spi1 with an SPI device.
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 64 ++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 46d9552f6028..a058a9e9d5d7 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -39,6 +39,10 @@ aliases {
serial7 = &uart7;
serial8 = &uart8;
serial9 = &uart9;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
};
cpus {
@@ -742,6 +746,66 @@ wdt: watchdog@fe600000 {
clock-names = "tclk", "pclk";
};
+ spi0: spi@fe610000 {
+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xfe610000 0x0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 20>, <&dmac0 21>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@fe620000 {
+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xfe620000 0x0 0x1000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 22>, <&dmac0 23>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@fe630000 {
+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xfe630000 0x0 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 24>, <&dmac0 25>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi3: spi@fe640000 {
+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xfe640000 0x0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 26>, <&dmac0 27>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart1: serial@fe650000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe650000 0x0 0x100>;
--
2.34.1
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next prev parent reply other threads:[~2021-11-27 14:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-27 14:19 [PATCH v2 0/3] RK356x/Quartz64 Model A SPI Nicolas Frattaroli
2021-11-27 14:19 ` [PATCH v2 1/3] dt-bindings: spi: spi-rockchip: Add rk3568-spi compatible Nicolas Frattaroli
2021-11-29 12:01 ` Mark Brown
2021-11-27 14:19 ` Nicolas Frattaroli [this message]
2021-11-27 14:19 ` [PATCH v2 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A Nicolas Frattaroli
2021-11-27 15:29 ` Johan Jonker
2021-11-27 15:40 ` Nicolas Frattaroli
2021-12-12 12:40 ` (subset) [PATCH v2 0/3] RK356x/Quartz64 Model A SPI Heiko Stuebner
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