From: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
To: Joel Stanley <joel@jms.id.au>, Rob Herring <robh+dt@kernel.org>,
"Andrew Jeffery" <andrew@aj.id.au>,
Linus Walleij <linus.walleij@linaro.org>
Cc: Jamie Iles <quic_jiles@quicinc.com>,
Graeme Gregory <quic_ggregory@quicinc.com>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-aspeed@lists.ozlabs.org>,
Johnny Huang <johnny_huang@aspeedtech.com>,
Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Subject: [PATCH 3/5] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group
Date: Mon, 7 Mar 2022 16:37:43 -0800 [thread overview]
Message-ID: <20220308003745.3930607-4-quic_jaehyoo@quicinc.com> (raw)
In-Reply-To: <20220308003745.3930607-1-quic_jaehyoo@quicinc.com>
From: Johnny Huang <johnny_huang@aspeedtech.com>
Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support
AST2600 FW SPI quad mode. These pins can be used with dedicated FW
SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14)
and FWSPIMISO (AB13).
Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
index 54064714d73f..80838dc54b3a 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
@@ -1236,12 +1236,17 @@ FUNC_GROUP_DECL(SALT8, AA12);
FUNC_GROUP_DECL(WDTRST4, AA12);
#define AE12 196
+SIG_EXPR_LIST_DECL_SESG(AE12, FWSPIQ2, FWQSPI, SIG_DESC_SET(SCU438, 4));
SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4);
-PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4));
+PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIQ2),
+ SIG_EXPR_LIST_PTR(AE12, GPIOY4));
#define AF12 197
+SIG_EXPR_LIST_DECL_SESG(AF12, FWSPIQ3, FWQSPI, SIG_DESC_SET(SCU438, 5));
SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5);
-PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5));
+PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIQ3),
+ SIG_EXPR_LIST_PTR(AF12, GPIOY5));
+FUNC_GROUP_DECL(FWQSPI, AE12, AF12);
#define AC12 198
SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6));
@@ -1911,6 +1916,7 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = {
ASPEED_PINCTRL_GROUP(FSI2),
ASPEED_PINCTRL_GROUP(FWSPIABR),
ASPEED_PINCTRL_GROUP(FWSPID),
+ ASPEED_PINCTRL_GROUP(FWQSPI),
ASPEED_PINCTRL_GROUP(FWSPIWP),
ASPEED_PINCTRL_GROUP(GPIT0),
ASPEED_PINCTRL_GROUP(GPIT1),
@@ -2152,6 +2158,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
ASPEED_PINCTRL_FUNC(FSI2),
ASPEED_PINCTRL_FUNC(FWSPIABR),
ASPEED_PINCTRL_FUNC(FWSPID),
+ ASPEED_PINCTRL_FUNC(FWQSPI),
ASPEED_PINCTRL_FUNC(FWSPIWP),
ASPEED_PINCTRL_FUNC(GPIT0),
ASPEED_PINCTRL_FUNC(GPIT1),
--
2.25.1
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next prev parent reply other threads:[~2022-03-08 0:39 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-08 0:37 [PATCH 0/5] Fix AST2600 quad mode SPI pinmux settings Jae Hyun Yoo
2022-03-08 0:37 ` [PATCH 1/5] ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi Jae Hyun Yoo
2022-03-08 0:37 ` [PATCH 2/5] pinctrl: pinctrl-aspeed-g6: " Jae Hyun Yoo
2022-03-08 0:37 ` Jae Hyun Yoo [this message]
2022-03-16 3:33 ` [PATCH 3/5] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group Andrew Jeffery
2022-03-16 5:05 ` Jae Hyun Yoo
2022-03-16 5:45 ` Andrew Jeffery
2022-03-16 6:03 ` Jae Hyun Yoo
2022-03-16 6:11 ` Andrew Jeffery
2022-03-08 0:37 ` [PATCH 4/5] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi Jae Hyun Yoo
2022-03-08 0:37 ` [PATCH 5/5] ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group Jae Hyun Yoo
2022-03-17 1:11 ` [PATCH 0/5] Fix AST2600 quad mode SPI pinmux settings Linus Walleij
2022-03-17 1:17 ` Joel Stanley
2022-03-24 19:11 ` Linus Walleij
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