From: Chris Packham <chris.packham@alliedtelesis.co.nz>
To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org,
davem@davemloft.net, kuba@kernel.org, linus.walleij@linaro.org,
catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch,
gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com,
adrian.hunter@intel.com, thomas.petazzoni@bootlin.com,
kostap@marvell.com, robert.marko@sartura.hr
Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Chris Packham <chris.packham@alliedtelesis.co.nz>
Subject: [PATCH v2 3/8] dt-bindings: mmc: xenon: add AC5 compatible string
Date: Tue, 15 Mar 2022 10:31:38 +1300 [thread overview]
Message-ID: <20220314213143.2404162-4-chris.packham@alliedtelesis.co.nz> (raw)
In-Reply-To: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz>
Import binding documentation from the Marvell SDK which adds
marvell,ac5-sdhci compatible string and documents the requirements for
the for the Xenon SDHCI controller on the 98DX2530.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- New
.../bindings/mmc/marvell,xenon-sdhci.txt | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
index c51a62d751dc..43df466f0cb3 100644
--- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
@@ -14,6 +14,7 @@ Required Properties:
- "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
- "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
- "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
+ - "marvell,ac5-sdhci": For CnM on AC5, AC5X and derived.
- clocks:
Array of clocks required for SDHC.
@@ -33,6 +34,13 @@ Required Properties:
in below.
Please also check property marvell,pad-type in below.
+ * For "marvell,ac5-sdhci", one or two register areas.
+ (reg-names "ctrl" & "decoder").
+ The first one is mandatory for the Xenon IP registers.
+ The second one is for systems where DMA mapping is required and is the
+ related address decoder register (the value to configure is derived from
+ the parent "dma-ranges").
+
* For other compatible strings, one register area for Xenon IP.
Optional Properties:
@@ -171,3 +179,47 @@ Example:
marvell,pad-type = "sd";
};
+
+
+- For eMMC with compatible "marvell,ac5-sdhci" with one reg range (no dma):
+ sdhci0: sdhci@805c0000 {
+ compatible = "marvell,ac5-sdhci";
+ reg = <0x0 0x805c0000 0x0 0x300>;
+ reg-names = "ctrl", "decoder";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&core_clock>;
+ clock-names = "core";
+ status = "okay";
+ bus-width = <8>;
+ /*marvell,xenon-phy-slow-mode;*/
+ non-removable;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ };
+
+- For eMMC with compatible "marvell,ac5-sdhci" with two reg ranges (with dma):
+ mmc_dma: mmc-dma-peripherals@80500000 {
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+ dma-ranges = <0x2 0x0 0x2 0x80000000 0x1 0x0>;
+ dma-coherent;
+
+ sdhci0: sdhci@805c0000 {
+ compatible = "marvell,ac5-sdhci", "marvell,armada-ap806-sdhci";
+ reg = <0x0 0x805c0000 0x0 0x300>, <0x0 0x80440230 0x0 0x4>;
+ reg-names = "ctrl", "decoder";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&core_clock>;
+ clock-names = "core";
+ status = "okay";
+ bus-width = <8>;
+ /*marvell,xenon-phy-slow-mode;*/
+ non-removable;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ };
+ };
--
2.35.1
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next prev parent reply other threads:[~2022-03-14 21:35 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-14 21:31 [PATCH v2 0/8] arm64: mvebu: Support for Marvell 98DX2530 (and variants) Chris Packham
2022-03-14 21:31 ` [PATCH v2 1/8] dt-bindings: pinctrl: mvebu: Document bindings for AC5 Chris Packham
2022-03-15 0:07 ` Andrew Lunn
2022-03-15 0:22 ` Chris Packham
2022-03-15 0:27 ` Andrew Lunn
2022-03-23 18:34 ` Rob Herring
2022-03-15 10:46 ` Krzysztof Kozlowski
2022-03-15 21:12 ` Chris Packham
2022-03-16 8:16 ` Krzysztof Kozlowski
2022-03-16 20:21 ` Chris Packham
2022-03-17 7:26 ` Krzysztof Kozlowski
2022-03-17 14:14 ` Andrew Lunn
2022-03-17 15:16 ` Krzysztof Kozlowski
2022-03-14 21:31 ` [PATCH v2 2/8] dt-bindings: net: mvneta: Add marvell,armada-ac5-neta Chris Packham
2022-03-15 0:10 ` Andrew Lunn
2022-03-14 21:31 ` Chris Packham [this message]
2022-03-15 0:14 ` [PATCH v2 3/8] dt-bindings: mmc: xenon: add AC5 compatible string Andrew Lunn
2022-03-14 21:31 ` [PATCH v2 4/8] pinctrl: mvebu: pinctrl driver for 98DX2530 SoC Chris Packham
2022-03-15 0:16 ` Andrew Lunn
2022-03-15 10:49 ` Krzysztof Kozlowski
2022-03-15 14:33 ` Andrew Lunn
2022-03-15 14:39 ` Krzysztof Kozlowski
2022-03-14 21:31 ` [PATCH v2 5/8] net: mvneta: Add support for 98DX2530 Ethernet port Chris Packham
2022-03-15 0:12 ` Andrew Lunn
2022-03-15 0:27 ` Chris Packham
2022-03-14 21:31 ` [PATCH v2 6/8] mmc: xenon: add AC5 compatible string Chris Packham
2022-03-15 0:14 ` Andrew Lunn
2022-03-14 21:31 ` [PATCH v2 7/8] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Chris Packham
2022-03-15 0:24 ` Andrew Lunn
2022-03-15 2:11 ` Chris Packham
2022-03-15 14:28 ` Andrew Lunn
2022-03-16 11:49 ` Marc Zyngier
2022-03-14 21:31 ` [PATCH v2 8/8] arm64: marvell: enable the 98DX2530 pinctrl driver Chris Packham
2022-03-15 0:25 ` Andrew Lunn
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